Insights on AI, Kubernetes, Ansible, cloud infrastructure, and automation by Luca Berton. https://lucaberton.com en-us Tue, 16 Jun 2026 22:07:45 GMT luca@lucaberton.com (Luca Berton) luca@lucaberton.com (Luca Berton) https://lucaberton.com/opengraph.jpg https://lucaberton.com https://lucaberton.com/blog/build-risc-v-toolchain-gcc-llvm/ https://lucaberton.com/blog/build-risc-v-toolchain-gcc-llvm/ How to build or install a RISC-V cross-compiler with GCC and LLVM/Clang — newlib vs glibc, multilib, and compiling your first RV64 binary from scratch. Thu, 11 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/getting-started-risc-v-qemu-emulation-linux/ https://lucaberton.com/blog/getting-started-risc-v-qemu-emulation-linux/ Emulate a full RISC-V Linux system on your laptop with QEMU — no hardware required. A step-by-step guide to booting Ubuntu and running your first RV64 binary. Thu, 11 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/history-of-risc-v-berkeley-origins/ https://lucaberton.com/blog/history-of-risc-v-berkeley-origins/ Where did RISC-V come from? The story from a 2010 Berkeley summer project to a global open standard — the people, the philosophy, and why it succeeded. Thu, 11 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/risc-v-ai-accelerators-open-silicon-2026/ https://lucaberton.com/blog/risc-v-ai-accelerators-open-silicon-2026/ How RISC-V powers modern AI accelerators — from Tenstorrent's Blackhole to edge NPUs — and why the open ISA is becoming the control plane for AI chips. Thu, 11 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/risc-v-assembly-language-tutorial/ https://lucaberton.com/blog/risc-v-assembly-language-tutorial/ Learn RISC-V assembly from scratch — registers, instruction formats, and a working hello-world you can run in QEMU. A beginner-friendly intro to the open ISA. Thu, 11 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/risc-v-automotive-functional-safety/ https://lucaberton.com/blog/risc-v-automotive-functional-safety/ Why carmakers are betting on RISC-V — Quintauris, functional safety (ISO 26262), mixed-criticality, and what it takes to put an open ISA in a vehicle. Thu, 11 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/risc-v-boot-flow-opensbi-uboot-firmware/ https://lucaberton.com/blog/risc-v-boot-flow-opensbi-uboot-firmware/ How a RISC-V system boots — the SBI, OpenSBI, U-Boot, UEFI, and the journey from reset vector to a running Linux kernel, explained step by step. Thu, 11 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/risc-v-chisel-chipyard-hardware-design/ https://lucaberton.com/blog/risc-v-chisel-chipyard-hardware-design/ Want to build your own RISC-V chip? An intro to Chisel, Chipyard, and the open hardware-design flow — from RTL generators to an FPGA or tape-out. Start here. Thu, 11 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/risc-v-cryptography-extensions-scalar-vector/ https://lucaberton.com/blog/risc-v-cryptography-extensions-scalar-vector/ How RISC-V accelerates cryptography — the scalar crypto (Zk) and vector crypto extensions, AES/SHA instructions, constant-time guarantees, and entropy sources. Thu, 11 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/risc-v-datacenter-servers-sovereign-ai-2026/ https://lucaberton.com/blog/risc-v-datacenter-servers-sovereign-ai-2026/ RISC-V has reached the datacenter — cloud servers, 64-core CPUs, HPC clusters, and sovereign AI. Here's the state of server-grade open silicon in 2026. Thu, 11 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/risc-v-debugging-openocd-gdb-jtag/ https://lucaberton.com/blog/risc-v-debugging-openocd-gdb-jtag/ A practical guide to debugging RISC-V — GDB, OpenOCD, JTAG, the Debug Spec, and single-stepping real hardware or QEMU. From printf to breakpoints. Thu, 11 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/risc-v-development-boards-2026-guide/ https://lucaberton.com/blog/risc-v-development-boards-2026-guide/ From the VisionFive 2 to the Milk-V Jupiter and Banana Pi BPI-F3 — the best RISC-V development boards to buy in 2026, matched to budget and use case. Thu, 11 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/risc-v-economics-royalty-free-business-case/ https://lucaberton.com/blog/risc-v-economics-royalty-free-business-case/ The economics behind RISC-V — royalty-free licensing, supply-chain control, customization, and why the business case (not just the tech) is driving adoption. Thu, 11 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/risc-v-ecosystem-2026-vendors-profiles-momentum/ https://lucaberton.com/blog/risc-v-ecosystem-2026-vendors-profiles-momentum/ The vendors, profiles, software, and momentum behind RISC-V in 2026 — a map of the open-silicon ecosystem and why it has reached an inflection point. Thu, 11 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/risc-v-embedded-iot-microcontroller-guide/ https://lucaberton.com/blog/risc-v-embedded-iot-microcontroller-guide/ RISC-V already ships in billions of embedded cores. A practical guide to RISC-V microcontrollers — ESP32-C, CH32V, PMP, the M-profile, and getting started. Thu, 11 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/risc-v-european-digital-sovereignty/ https://lucaberton.com/blog/risc-v-european-digital-sovereignty/ Why RISC-V is central to Europe's digital sovereignty strategy — from the EU Chips Act and EuroHPC to Quintauris, BSC, and sovereign AI in 2026. Thu, 11 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/risc-v-extensions-explained-isa-alphabet/ https://lucaberton.com/blog/risc-v-extensions-explained-isa-alphabet/ M, A, F, D, C, V, B, H and the Z-extensions — a clear guide to the RISC-V extension alphabet and how to read strings like RV64GC and rv64imafdc. Thu, 11 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/risc-v-hpc-supercomputing-european-processor/ https://lucaberton.com/blog/risc-v-hpc-supercomputing-european-processor/ RISC-V is heading for the supercomputer — Monte Cimone, the European Processor Initiative, and what it takes to build HPC on an open ISA. Thu, 11 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/risc-v-interrupts-plic-clint-aia/ https://lucaberton.com/blog/risc-v-interrupts-plic-clint-aia/ How interrupts work on RISC-V — traps, the CLINT and PLIC, and the modern Advanced Interrupt Architecture (AIA) with MSIs. A guide for systems devs. Thu, 11 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/risc-v-linux-distributions-guide/ https://lucaberton.com/blog/risc-v-linux-distributions-guide/ Yes, you can run a full Linux desktop and server on RISC-V today. A practical guide to Ubuntu, Fedora, and Debian on RISC-V — and how mature each really is. Thu, 11 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/risc-v-memory-model-atomics-rvwmo/ https://lucaberton.com/blog/risc-v-memory-model-atomics-rvwmo/ Understand the RISC-V memory model (RVWMO), atomic instructions, LR/SC, and fences. A practical guide to concurrency and lock-free programming on RISC-V. Thu, 11 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/risc-v-open-source-cores-cva6-xiangshan/ https://lucaberton.com/blog/risc-v-open-source-cores-cva6-xiangshan/ A tour of the leading open-source RISC-V cores — CVA6, XiangShan, lowRISC Ibex, and the PULP platform — and why open silicon all the way down matters. Thu, 11 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/risc-v-profiles-rva23-explained/ https://lucaberton.com/blog/risc-v-profiles-rva23-explained/ Why RISC-V profiles exist and what RVA23 changes — the standardized extension bundles that make 'write once, run anywhere' real for RISC-V software. Thu, 11 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/risc-v-security-privilege-pmp-confidential-computing/ https://lucaberton.com/blog/risc-v-security-privilege-pmp-confidential-computing/ How RISC-V handles security — machine/supervisor/user privilege, Physical Memory Protection, the hypervisor extension, and confidential computing. Thu, 11 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/risc-v-software-porting-ecosystem/ https://lucaberton.com/blog/risc-v-software-porting-ecosystem/ How to port applications and libraries to RISC-V — cross-compiling, common pitfalls, intrinsics, CI, and the state of the riscv64 software ecosystem in 2026. Thu, 11 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/risc-v-space-aerospace-radiation-hardened/ https://lucaberton.com/blog/risc-v-space-aerospace-radiation-hardened/ Why space agencies are adopting RISC-V — NASA's HPSC, radiation hardening, fault tolerance, and the case for an open ISA in satellites and spacecraft. Thu, 11 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/risc-v-vector-extension-rvv-programming/ https://lucaberton.com/blog/risc-v-vector-extension-rvv-programming/ A hands-on introduction to the RISC-V Vector extension (RVV 1.0) — the vector-length-agnostic model, key instructions, and a worked SAXPY example you can run. Thu, 11 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/risc-v-virtualization-hypervisor-kvm/ https://lucaberton.com/blog/risc-v-virtualization-hypervisor-kvm/ How virtualization works on RISC-V — the hypervisor (H) extension, two-stage translation, KVM, and running virtual machines on open silicon. A systems guide. Thu, 11 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/risc-v-vs-arm-vs-x86-isa-comparison/ https://lucaberton.com/blog/risc-v-vs-arm-vs-x86-isa-comparison/ How RISC-V stacks up against ARM and x86 on licensing, performance, software maturity, and customization — and where each architecture wins in 2026. Thu, 11 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/what-is-risc-v-open-isa-explained/ https://lucaberton.com/blog/what-is-risc-v-open-isa-explained/ A plain-English introduction to RISC-V — the free, open instruction set architecture reshaping chips from microcontrollers to datacenter servers. Thu, 11 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/risc-v-abi-calling-convention/ https://lucaberton.com/blog/risc-v-abi-calling-convention/ How RISC-V code actually fits together — registers, the psABI, argument passing, the stack, and ILP32 vs LP64. A practical guide to the calling convention. Thu, 11 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/risc-v-embedded-rust-programming/ https://lucaberton.com/blog/risc-v-embedded-rust-programming/ Rust and RISC-V are a natural pair. How to write embedded Rust for RISC-V microcontrollers — targets, no_std, PACs, HALs, and flashing real hardware. Thu, 11 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/risc-v-floating-point-extensions/ https://lucaberton.com/blog/risc-v-floating-point-extensions/ How RISC-V does floating-point — the F, D, and Q extensions, the f registers, rounding modes, and lightweight options like Zfh and Zfinx for small cores. Thu, 11 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/risc-v-fpga-softcore-tutorial/ https://lucaberton.com/blog/risc-v-fpga-softcore-tutorial/ Turn a cheap FPGA into a real RISC-V CPU. A practical intro to softcores like PicoRV32 and VexRiscv — what they are, how the flow works, and how to start. Thu, 11 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/risc-v-performance-profiling-counters/ https://lucaberton.com/blog/risc-v-performance-profiling-counters/ Make RISC-V code fast — hardware performance counters (HPM), the cycle and instret CSRs, perf on Linux, and a sane workflow for finding real bottlenecks. Thu, 11 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/risc-v-zephyr-rtos-guide/ https://lucaberton.com/blog/risc-v-zephyr-rtos-guide/ Zephyr is the open RTOS of choice for modern RISC-V microcontrollers. What Zephyr is, why it fits RISC-V, and how its build and driver model work. Thu, 11 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/risc-v-containers-kubernetes-cloud-native/ https://lucaberton.com/blog/risc-v-containers-kubernetes-cloud-native/ Yes, RISC-V runs Docker and Kubernetes. How container images, multi-arch builds, and the cloud-native stack work on RISC-V — and what's still maturing. Thu, 11 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/building-reliable-ai-agents-java-langchain4j-workshop-2026/ https://lucaberton.com/blog/building-reliable-ai-agents-java-langchain4j-workshop-2026/ Packt workshop with Susanne Pieterse on building production-ready AI agents in Java with LangChain4J — guardrails, evaluation, observability. June 13, 2026. Wed, 10 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) AI https://lucaberton.com/blog/one-student-one-chip-risc-v-bosc-open-education-2026/ https://lucaberton.com/blog/one-student-one-chip-risc-v-bosc-open-education-2026/ BOSC's One Student One Chip teaches students to design RISC-V processors from ISA to GDSII tape-out. At RISC-V Summit Europe 2026, 18,861 enrollments revealed. Wed, 10 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/openclaw-err-string-too-long-bloated-session-fix/ https://lucaberton.com/blog/openclaw-err-string-too-long-bloated-session-fix/ OpenClaw agent fails with 'Cannot create a string longer than 0x1fffffe8 characters'? It's a bloated session JSONL hitting Node's string limit. Here's the fix. Wed, 10 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) DevOps https://lucaberton.com/blog/risc-v-summit-europe-2026-bologna-highlights/ https://lucaberton.com/blog/risc-v-summit-europe-2026-bologna-highlights/ My experience at RISC-V Summit Europe 2026 in Bologna — from Tenstorrent Blackhole to Monte Cimone v3 HPC, ESWIN server CPUs, and open-silicon research. Wed, 10 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/risc-v-summit-europe-2026-bologna-open-hardware-ai/ https://lucaberton.com/blog/risc-v-summit-europe-2026-bologna-open-hardware-ai/ On-the-ground coverage from RISC-V Summit Europe 2026 in Bologna — SiFive, ETH Zurich, Qualcomm, and Luxottica on open silicon for AI and smart eyewear. Wed, 10 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/chloe-jian-ma-epic-semi-risc-v-ai-server-ubuntu/ https://lucaberton.com/blog/chloe-jian-ma-epic-semi-risc-v-ai-server-ubuntu/ At RISC-V Summit Europe 2026 I met Chloe Jian Ma of EPIC Semi to discuss the first RISC-V AI server — 48 cores, 16 AI cores, and Ubuntu booting live. Wed, 10 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/omnitrust-ai-trust-visibility-control-transparency/ https://lucaberton.com/blog/omnitrust-ai-trust-visibility-control-transparency/ At RISC-V Summit Europe 2026 I met Toby from OmniTrust, building an ecosystem of visibility, control and transparency so AI can speed up innovation safely. Wed, 10 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/frederik-high-tech-startup-strategy-go-to-market/ https://lucaberton.com/blog/frederik-high-tech-startup-strategy-go-to-market/ At RISC-V Summit Europe 2026 I met Frederik on the business side of deep tech — go-to-market, market strategy, and a playbook to grow from unknown to player. Wed, 10 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/tenstorrent-blackhole-tensix-risc-v-ai-scale/ https://lucaberton.com/blog/tenstorrent-blackhole-tensix-risc-v-ai-scale/ A floor tour at RISC-V Summit Europe 2026 showing how RISC-V now scales from small embedded dev boards to Tenstorrent AI compute and Scaleway servers. Wed, 10 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/inspiresemi-nextsilicon-risc-v-hpc-floor/ https://lucaberton.com/blog/inspiresemi-nextsilicon-risc-v-hpc-floor/ A show-floor look at RISC-V Summit Europe 2026: InspireSemi's RISC-V supercomputing accelerators and NextSilicon's high-performance compute for HPC and AI. Wed, 10 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) RISC-V https://lucaberton.com/blog/google-search-console-growth-analysis-python-script-2026/ https://lucaberton.com/blog/google-search-console-growth-analysis-python-script-2026/ Run one dependency-free Python script on your Search Console export to surface the SEO levers that move traffic: CTR bands and striking-distance pages. Sun, 07 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) DevOps https://lucaberton.com/blog/ai-gateway-kubernetes-routing-load-balancing-2026/ https://lucaberton.com/blog/ai-gateway-kubernetes-routing-load-balancing-2026/ Deploy an AI gateway on Kubernetes for intelligent LLM request routing, model fallback, rate limiting, cost tracking, and multi-provider load balancing. Fri, 05 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) AI https://lucaberton.com/blog/ai-model-serving-kubernetes-vllm-triton-nim-2026/ https://lucaberton.com/blog/ai-model-serving-kubernetes-vllm-triton-nim-2026/ Compare vLLM, Triton Inference Server, and NVIDIA NIM for serving LLMs on Kubernetes. Throughput benchmarks, deployment patterns, and production configuration. Fri, 05 Jun 2026 00:00:00 GMT luca@lucaberton.com (Luca Berton) AI