RISC-V is not just a development board anymore. Here is a quick floor tour from RISC-V Summit Europe 2026 in Bologna, showing just how broad the RISC-V hardware story has become — from small embedded development boards all the way up to AI and the server side.
The Whole Spectrum, in One Walk-Through
The takeaway from the tour is how far RISC-V now reaches. A few years ago the conversation was mostly about small boards and microcontrollers; today the same open ISA runs across learning hardware, edge AI, and production servers. Highlights from the walk:
- Small, accessible development boards for getting started — the entry point for engineers and students.
- AI compute powered by Tenstorrent — bringing serious AI acceleration onto open silicon.
- Multi-node and server-class deployments with Scaleway — RISC-V showing up as real datacenter infrastructure.
- A growing line-up of familiar silicon manufacturers across the ecosystem.
From Learning Hardware to Production AI
The most striking part is the continuity. The same architecture that lives on an accessible development board is the architecture that scales out across multiple nodes on the server side. That “one architecture, prototype to data center” story is exactly what makes open silicon compelling — you are not throwing away your software stack when you move from experimentation to production.
A Growing Field of Players
This is not happening in isolation. From Tenstorrent’s AI compute to Scaleway’s server-class deployments, plus SiFive and a growing line-up of familiar silicon vendors and education efforts like One Student One Chip feeding the talent pipeline, more pieces are evolving in parallel — and they reinforce each other.
The Sovereign Angle
As with so much at this Summit, the throughline is sovereignty. Hardware built on open RISC-V silicon gives organizations and nations a path to homegrown, inspectable, controllable infrastructure — the hardware counterpart to Europe’s digital-sovereignty agenda.
The Bottom Line
The floor tour makes one thing clear: RISC-V now scales across the whole spectrum, from learning hardware to production AI infrastructure. With Tenstorrent driving AI compute, Scaleway running it at server scale, and a deep bench of manufacturers behind embedded boards, open silicon has grown from a curiosity into a real, end-to-end hardware story.
Recorded at RISC-V Summit Europe 2026, Bologna, Italy, 8–12 June 2026. Part of my RISC-V series — see also the Summit highlights and RISC-V AI accelerators & open silicon.
