One of the best conversations I had at RISC-V Summit Europe 2026 in Bologna was not with a chip company or a cloud provider. It was with Dan, a RISC-V International advocate who showed up with a board his student team had designed — and actually had fabricated and assembled.
That last part is what makes it interesting.
The Board: Gowin FPGA + RP2350
The SemiTo-V team built a board that pairs two chips with complementary strengths:
- Gowin FPGA — a mid-range, cost-accessible FPGA that supports RISC-V soft cores. Gowin’s devices have become popular in the open hardware community for their price-to-capability ratio and the quality of their open toolchain support.
- RP2350 MCU — Raspberry Pi’s dual-core microcontroller (the successor to the RP2040), which includes two ARM Cortex-M33 cores and two RISC-V Hazard3 cores that can be run in place of the ARM cores. The flexibility to switch between ISAs on the same silicon is unusual and useful for experimenting with RISC-V execution at the MCU level.
Together, the board gives students a platform for exploring RISC-V at two levels simultaneously: as a soft core implemented in FPGA fabric, and as a hardware implementation in the RP2350’s RISC-V execution cores. That is a genuinely useful combination for anyone learning processor architecture from the ground up.
From Design to Physical Board
The student team behind this is SemiTo-V, with Dan collaborating as an open-source contributor. The design process went through the standard stages: schematic, layout, design rule checks, and file preparation for manufacturing.
What made the fabrication possible was NextPCB’s free PCBA sample program. NextPCB offers qualified open-source projects free printed circuit board assembly — which means not just bare boards but boards with all components soldered. For a student team without a sponsorship budget, this closes the gap between “we designed something” and “we have a working thing we can hand to someone.”
The result was a functional board that Dan was able to bring to Bologna and demonstrate in person. That physical artifact — not a render, not a simulation, but an actual assembled board — is what the open hardware ecosystem is supposed to enable.
The Gowin Ecosystem at the Summit
Dan also had a broader Gowin showcase at the booth, including:
- Tang Primer 25K — a compact development board built around Gowin’s GW5A FPGA, popular for RISC-V core experimentation and retro-computing projects
- Tang Mega boards — larger Gowin boards based on the Arora FPGA family, with up to approximately 128,000 lookup tables and a hard processor core clocked near 1 GHz
The Arora family’s embedded hard core changes the calculus for FPGA-based RISC-V work: instead of spending all your LUT budget on a soft CPU, you can run control logic on the hard core and dedicate the programmable fabric to custom accelerators, peripherals, or co-processors. That is the pattern that serious FPGA-based RISC-V projects increasingly use.
What Struck Dan About the Summit
When I asked Dan what stood out about RISC-V Summit Europe 2026, his answer was about the breadth of the community rather than any specific announcement: RISC-V now brings together the whole stack in one room.
That observation is easy to underestimate. Most technical conferences attract one layer of the stack — chip designers, or software developers, or platform engineers. RISC-V Summit brings all of them together because the open ISA creates shared interest across layers that would otherwise not have a natural gathering point. The person designing a custom RISC-V core for automotive safety, the student implementing one on an FPGA, and the platform engineer running RISC-V workloads on Kubernetes are all working in the same ecosystem and have reasons to talk to each other.
That is what an open standard enables beyond the technical specification itself.
Why Student Hardware Projects Matter
The SemiTo-V board is a small thing — one board, one student team, one fabrication run. But it represents something the RISC-V ecosystem needs at scale: people learning chip design by doing it, not just by reading about it.
The One Student One Chip initiative at the same summit is targeting the same gap from a different angle — taking students all the way through chip tapeout for free. SemiTo-V is doing it at the FPGA and PCB level. Both are necessary because the pipeline from “student interested in hardware” to “engineer contributing to open silicon” requires on-ramps at every difficulty level.
The gap right now is not talent or interest. It is the infrastructure to convert that interest into real, physical experience with real hardware. Programs like NextPCB’s PCBA offer and initiatives like RISC-V International’s education focus are the infrastructure layer that makes that conversion possible.
Related Coverage from RISC-V Summit Europe 2026
- DeepComputing DC-ROMA: DeepSeek on a RISC-V Laptop
- One Student One Chip: Free Tapeouts for RISC-V Education
- EPIC Semi’s First RISC-V AI Server Runs Ubuntu
- RISC-V Summit Europe 2026: Bologna Highlights
- RISC-V Development Boards 2026 Guide
About the Author
I am Luca Berton, AI and Cloud Advisor. I cover the intersection of open hardware and production AI infrastructure. Book a consultation.
