On Thursday 7 August 2025 I attended World RISC-V Days in Hanoi, Vietnam. The slide on the screen said it all: âThursday, August 7, 2:00pm - 4:00pm, Hanoi University of Science and Technologyâ, with the universityâs School of Electrical and Electronic Engineering as the host named at the top. The session was held in the universityâs large conference hall, and the programme was a run of short talks, each on a different corner of the RISC-V world: a company building products, a security talk, a university research institute, a privacy company betting on open hardware, and a closing talk on AI and chip design.
I was there as an attendee. Iâm not on the agenda, and no slide lists me as a speaker. I work with DeepComputing on RISC-V, so the first talk was the one I was most curious about, but I took photos of every talk and this post follows them in order.
The title slide before the first talk: World RISC-V Days, Hanoi, Vietnam, 2:00pm to 4:00pm.
DeepComputingâs RISC-V Innovation Journey
The first talk was titled âDeepComputingâs RISC-V Innovation Journeyâ and the slide is dated July 2025. The name card on the table in front of the speakerâs seat reads âDr. Yuning Liangâ, âFounderâ for Deep Computing. The slideâs own text names him as the presenter.
DeepComputingâs âRISC-V Innovation Journeyâ title slide.
The founder opened by telling the students, mostly young people in the hall, that they are the future of RISC-V, and then explained how DeepComputing got started. Here is what he said, in my words:
- Why a laptop. He called himself a software and compiler person, not a hardware person. His compiler business hit a deadlock: system software waited for chips, and chip makers would not buy a compiler for a processor nobody used. To break the cycle he decided to build hardware himself. He chose the laptop because the volume is big enough and the story is easy to tell, and because a mobile phone was out of reach (the modem market is held by two big vendors, and the first chip was a 12 nm part).
- The first laptop. The first chip was a 12 nm test chip. Friends in Shenzhen who make laptops for x86 vendors had never designed one from scratch, because the chip vendor supplies nearly everything. The first RISC-V laptop sold for about five thousand dollars, and he joked it will be worth much more in twenty years. He joked that a friend called Peter bought one and then spent months chasing him for newer ones.
- Software support. In the early days there was no official Linux support for RISC-V. The first laptop shipped with Debian. He recalled that Canonicalâs commercial team once asked for a large sum to support a RISC-V board; he declined, and in 2024 got Ubuntu on the second laptop without paying, by offering visibility instead of money.
- Framework. After two laptops of his own, he said he was tired of building whole laptops and partnered with Framework, so that DeepComputing now makes mainboards that fit the repairable, upgradable Framework chassis. He described a 50 TOPS AI-PC board that, according to him, can run a 14B-parameter language model, and invited people to join the open-source compiler work.
- Why open ISA. His historical argument was that x86 grew up closed and American, ARM is âhalfway openâ (anyone can make an SoC, but one company owns the ISA and can withdraw a licence), and RISC-V is an instruction set owned by no company or country. He mentioned that Europe and China are both adopting it hard.
My take: the deadlock he described (software waits for hardware, hardware waits for software) is the best short explanation I have heard of why RISC-V took so long, and why a vendor shipping real, usable machines matters more than another benchmark.
DeepComputingâs website describes the company as building RISC-V computing hardware. The DC-ROMA line includes mainboards compatible with the Framework Laptop 13, plus RISC-V laptops and tablets. I saw the same team again at their booth in Amsterdam a few weeks later, which I wrote up in the Open Source Summit Europe 2025 recap. For more on their hardware, see the DC-ROMA post and OpenBao on RISC-V.
Applications of RISC-V SoC in enhancing security of embedded systems
The second talk was âApplications of RISC-V SoC in enhancing security of embedded systemâ, presented by Dr. Dao Ba Anh of the Academy of Cryptography Techniques, as named on the title slide, which is dated 8/7/2025 and tagged âRISC-V Days Hanoi 2025â.
The embedded-security talk from the Academy of Cryptography Techniques.
The speaker began with the academy itself: it has a main campus in Hanoi and a branch in Ho Chi Minh City, with undergraduate programmes in information security, embedded and mobile programming and embedded systems and IC design, and masterâs and doctoral programmes in information security and cryptography. The talk then showed what you get when you treat a RISC-V SoC as a security platform:
- Crypto accelerators as peripherals. Because the core, the bus and the SoC framework are open, a team can add its own components. They put cryptographic accelerators next to an open RISC-V core, keeping software flexibility on the CPU and hardware speed in the peripheral. They implemented two block ciphers: an older one with 64-bit blocks and 4-bit S-boxes, and the Russian standard GOST R 34.12-2015 (Kuznyechik, âthe grasshopperâ), which is structured like AES with a 256-bit key and 128-bit blocks. For the second one the speaker reported an encryption speed-up of nearly 1,600 times over software, because the algorithm is expensive to run on a CPU.
- Side-channel defence. The speaker explained that AES is mathematically hard to break but a device running it can leak its key through power consumption or electromagnetic emission, which an attacker analyses statistically. Their countermeasure randomises the operating clock frequency of the crypto accelerator, so each encryption runs on a slightly different time frame and the attackerâs traces are misaligned. In evaluation, the unprotected SoC showed leakage in the TVLA test with only a few thousand traces, while the protected one showed none even after millions. In a correlation power analysis against AES-128 the attacker recovered the key bytes of the unprotected chip but not a single byte of the protected one, even with five million traces. A deep-learning-based attack still found some bytes, but needed far more traces, so the protection did raise the cost.
- An IoT use. The same SoC went into a secure IoT node: sensors, a LoRa radio, encrypted transmission from node to node to server, and a cloud dashboard, all on a mid-size Xilinx Artix-7 FPGA.
As I understood it, the argument is that open cores let a small university group do security research that would be impossible on a closed processor.
Its âMotivationâ slide compared three instruction set architectures side by side:
- x86 as a closed ISA, found in most desktops, laptops and servers with an Intel or AMD processor.
- ARM as a closed ISA, used in Android and iOS devices and in newer Apple computers.
- RISC-V as an open ISA, where, in the slideâs words, anybody can design and sell a RISC-V processor without constraints on their actions.
A column on the right listed what âopenâ means in practice: an open instruction set architecture, modular design with optional extensions, open-source processing cores and open-source SoC design frameworks. If you want the background, I explain the idea in What is RISC-V.
The âMotivationâ slide: x86 and ARM as closed ISAs, RISC-V as an open one.
RISC-V research at VNU-ITI
Next came âRISC-V Ecosystem Research and Development Activities at VNU-ITIâ from the VNU Information Technology Institute, part of Vietnam National University, Hanoi. The slide credits Manh-Hiep Dao, Duy-Hieu Bui and Xuan-Tu Tran of the Research Center for Integrated Circuits & Applications (CICA), and shows chip photos and a layout. I canât tell from the slide which of the three authors was at the microphone, so I wonât guess.
The VNU-ITI title slide: RISC-V ecosystem research and development activities.
The presenter described the lab, a team of several PhDs, PhD students, graduate students and undergraduates from different Hanoi universities, working on five topics: hardware security and security hardware, AI accelerators for edge devices, video processing, accelerators for FPGA platforms, and hardware/software co-design with RISC-V and open-source tools.
The RISC-V work started around 2017 with an IoT project: an in-house RISC-V processor with an AES encryption accelerator, a version of it taped out for a TSMC 65 nm process to measure power, and a demo node that logs temperature and humidity inside the institute. Everything in the toolchain (GCC, an Arduino-style SDK) is open. The lab later built a tiny neural-network core on an Artix-7 FPGA, published the results in two papers, and used Chipyard to generate multi-core RISC-V designs.
The speakerâs argument for RISC-V in IoT had four parts: it can be made multi-core for performance, its simple instruction set suits low-power techniques, it works well with hardware cryptography, and small AI models can run on it. On the ecosystem, they counted more than 100 RISC-V cores, of which over 40% have open-source licences, and said more than 80% of the SoC platforms can be reused. Their view was that this gives Vietnamese researchers a way to contribute without starting from zero.
A later slide listed the instituteâs collaborations, grouped into universities and research institutions, industrial collaborators and societies. The logos on it included Toshiba, Avnet, Keysight, Synopsys, Muse Semiconductor, TSMC and GlobalFoundries, plus several European and Asian universities and the IEEE Circuits and Systems Society.
The collaborations slide from the VNU-ITI talk.
Spoken alongside that slide: partners in France (Grenoble), Italy, the US, Sydney and Japan, long-standing ties with Toshiba, fabrication through TSMC and GlobalFoundries, and about twenty years of research and contribution to IEEE societies.
Open Hardware: Not If, But When
The title that stuck with me was âOpen Hardware: Not If, But Whenâ, subtitled âWhy ExpressVPN is Betting on RISC-V for Tomorrowâs Privacyâ. The slide names Peter Membrey, Chief Research Officer, and carries the ExpressVPN logo and a RISC-V Strategic Member badge.
âOpen Hardware: Not If, But Whenâ, with the ExpressVPN and RISC-V Strategic Member logos.
This was the talk I wanted most to write up, so here is the argument as he made it, with the usual caveat that it is a vendorâs view.
Backing the underdog. He opened with Linux: in 1991 a hobby, in 2000 still laughed at (he mentioned Microsoft calling it a hobbyist competitor and IBM investing a billion dollars in it), and today everywhere. His point is that ExpressVPN has a habit of building ahead of the curve. He listed the Lightway protocol (2020, fully open source, recently rewritten in Rust, designed mobile-first for limited CPU and battery), Trusted Server (an in-memory, immutable, cryptographically signed server OS with public audits), and hybrid post-quantum key exchange added to Lightway in 2023. He said the newest NIST ML-KEM standard was implemented in under a month, and called it the only VPN product with native post-quantum protection. The âstore now, decrypt laterâ threat was his reason.
Why hardware. The VPNâs apps, protocol and server design are open, but below that sit firmware and silicon that remain black boxes: management engines, possible backdoors. That does not mean something is wrong, but you cannot be sure it isnât, and a root of trust you cannot inspect is a problem.
The AI dilemma. He described âdoor oneâ (powerful cloud AI, with privacy only by policy) and âdoor twoâ (full privacy on-device, but weaker models), and asked where door three is. As an anecdote, not a controlled test, he said a senior engineerâs task that took about an hour and a half was done by Claudeâs latest model in under seven minutes.
The geopolitical argument. Stable supply chains and neutral technology are gone; export restrictions limit access to high-performance processors; and a few companies in practice control CPUs, GPUs and mobile chips. His answer was RISC-V as a way to verify the stack: give a government or industry the blueprints, and let them build and audit the chips and run open-source software on top.
The call to the students. Experiment now, even if it is not production-ready, because the people who know how to build this will be in demand. He called it Vietnamâs Linux moment and closed with a Seneca line about destiny guiding the willing and dragging the unwilling.
An ExpressVPN colleague then gave a short, practical talk on porting the Lightway protocol to RISC-V. Notes from it:
- Why businesses care: no licence fee, so low cost, and modularity (you can add your own extensions). He compared a RISC-V board favourably on price with a Raspberry Pi.
- What works: a pure Rust project needs little more than adding a target argument; Rust has tier 2 support, and Gentoo and QEMU were useful to point at when persuading a business owner.
- Pain points: Node.js has no official RISC-V build; there are few Docker images, which hurts container-based CI; VS Codeâs remote SSH does not work because it puts a binary on the target that isnât built for RISC-V; and GUI toolkits such as Qt lack official support.
- Advice: check that your dependencies support RISC-V, write a portable general version before any x86 assembly, and check whether inline assembly is needed at all because compilers are good now.
My take: the porting list is the most useful thing in the session for anyone running CI. If your build and debug tooling depends on container images and remote-IDE binaries, RISC-V support has to start there, long before the chips are fast enough.
My take: the privacy argument for open hardware is the same as for open source software. If you canât inspect the silicon, youâre trusting the vendor for the layer underneath all your other controls. Thatâs also why I find RISC-V interesting for secrets management and sovereign infrastructure.
From AI-generated chip design to emerging trends
The last talk I photographed was âRISC-Vâs Growing Impact: From AI-Generated Chip Design to Emerging Trends in Industryâ, with the line âPresenter: Lan Dang, World RISC-V Days - Hanoi, Vietnamâ on the title slide. A later slide quoted a newcomer engineer who was new to RISC-V and chip design and felt astonished by its progress and innovation.
The closing talk on AI-generated chip design and industry trends.
The quote on that later slide turns out to be the presenter describing himself: a newly graduated engineer with a year of FPGA experience who had built RISC-V and embedded prototypes and was astonished at how fast the field moves. His talk had two parts.
A case study in accessibility. A spiking-neural-network core, built by colleagues in the university lab as a fun side project, won first prize in an open-source chip design challenge that encourages the use of LLMs (here GPT-4o) to speed up design. The team extended an open-source RISC-V SoC with the AI-generated, verified component and wrote firmware for it, with handwritten digit recognition as the demo. He said the AI-generated RTL, combined with solid digital-design fundamentals, cut the RTL-to-GDSII flow to nearly a month. He was open that it is not a market-ready product; his point was that students and hobbyists can now take part in chip design.
Where RISC-V is going. He cited a market analysis by the SHD Group projecting RISC-V SoC shipments growing from 1.3 billion units in 2023 to 16.2 billion by 2030. He described China (with RISC-V members such as Alibaba and Tencent, and adoption as a response to export controls), Europe (reducing dependence on proprietary architectures, with named projects around digital autonomy), India (a national RISC-V programme since 2022) and the US (leading in design technology but with big incumbents in Arm and x86). He noted that NVIDIA announced CUDA support for RISC-V at a 2025 RISC-V event and that Western Digital released an open-source core years ago. Examples of real chips were SiFiveâs data-centre core scaling to 256 cores, the Sophgo SG2042 (64 cores, up to 2 GHz, 64 MB system cache) and T-Headâs C910, an out-of-order design reaching 2.5 GHz that runs full Linux and Android. His trend list: a shift from low-end embedded cores to high-performance and AI CPUs, many-core scaling for ML workloads, domain-specific processors for automotive and edge, and a growing software ecosystem. His closing message was that the lack of licence fees lowers the barrier for startups and for Vietnam to design competitive chips, and that students should go for RISC-V careers.
I left out the figures for European and Indian programmes: the recording was too unclear to quote them reliably.
What I took away
Looking back at the photos and the recordings, the mix of a hardware vendor, a cryptography academy, a research institute and a privacy company in a two-hour session is a good picture of how broad RISC-V has become: products, security, research and privacy all in one room.
