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Book signing at RISC-V Summit Europe 2026 in Bologna, Italy
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Book Signing at RISC-V Summit Europe 2026 in Bologna

Meet Luca Berton at RISC-V Summit Europe 2026 in Bologna, Italy. Get your signed copy of Kubernetes Recipes and discuss open hardware, AI infrastructure.

LB
Luca Berton
Β· 2 min read

I am excited to announce that I will be at RISC-V Summit Europe 2026 in Bologna, Italy β€” and I am bringing signed copies of Kubernetes Recipes!

RISC-V Summit Europe 2026

RISC-V is one of the most important movements in open computing: open standards, open collaboration, and a growing global ecosystem pushing innovation across hardware, software, AI, embedded systems, and cloud infrastructure.

The Summit brings together the entire RISC-V ecosystem β€” from silicon designers to software engineers β€” for keynotes, technical sessions, demos, and networking. This year features:

  • RISC-V State of the Union by Krste Asanovic (Chief Architect, RISC-V International / SiFive)
  • Security extensions and matrix extensions for AI
  • New profile and platform initiatives
  • Ecosystem showcases from hardware vendors, research labs, and open source projects

πŸ“ Bologna, Italy 🎟️ Registration

Book Signing

I will be on site during the Summit with copies of Kubernetes Recipes available for signing. Whether you are a hardware engineer curious about cloud-native orchestration, a platform engineer interested in RISC-V edge deployments, or just want to connect β€” come find me!

After years of working across Linux, automation, Kubernetes, cloud-native platforms, and open source communities, I am especially excited to see how RISC-V continues to connect silicon innovation with real-world software ecosystems.

What I would love to discuss:

  • Running Kubernetes on RISC-V hardware
  • AI inference at the edge on open hardware
  • Platform engineering for heterogeneous compute (x86 + ARM + RISC-V clusters)
  • The convergence of open hardware and open source software communities

Why RISC-V Matters for Cloud-Native

The RISC-V ISA is not just a chip architecture β€” it represents the same open philosophy that drives Linux, Kubernetes, and the entire cloud-native stack. As AI workloads push toward specialized hardware (NPUs, matrix engines, custom accelerators), having an open instruction set means:

  1. No vendor lock-in at the silicon level
  2. Custom extensions for AI/ML workloads without licensing fees
  3. Security extensions designed in the open, auditable by everyone
  4. Edge-to-cloud consistency β€” same ISA from microcontrollers to datacenter chips

The RISC-V ecosystem is maturing rapidly. We are already seeing production Kubernetes clusters running on RISC-V boards, and the software toolchain (GCC, LLVM, Linux kernel support) is production-ready for many use cases.

See You in Bologna

If you are attending RISC-V Summit Europe 2026, reach out β€” I would love to meet, sign your book, and hear what you are building on open hardware.

Free 30-min AI & Cloud consultation

Book Now