RISC-V Summit Europe 2026 — Bologna, Italy
I attended the RISC-V Summit Europe 2026 in Bologna (June 8-12), the premier European event for the open instruction set architecture that’s reshaping computing from embedded to data center. With one-third of RISC-V’s global community based in Europe, this was the place to be.
Here’s my on-the-ground coverage of the highlights.
Wednesday Morning Plenary Schedule
The Wednesday morning plenary packed heavyweight talks back-to-back:
- 9:00 — RISC-V State of the Union (Krste Asanović)
- 9:30 — Nuclei: Full-Spectrum RISC-V IP and Automated SoC Design (Bob Hu)
- 9:45 — ARBEL: The Leading Server-Class RISC-V CPU (Yiftach Gilad)
- 10:00 — RISC-V: Enabling Open Physical AI (Luca Benini)
- 11:30 — From Eyewear to Silicon: Low-Power AI in Smart Glasses (Marco Fariselli, Luxottica)
- 12:00 — RVEdge-Vision: Ultra-Efficient On-Device AI for Smart Eyewear (Michele Magno)
- 12:15 — RIVIERA: Programmable RISC-V Edge Architecture for NFC (Luca Lingardo)
- 12:30 — Accelerating RISC-V with open MPACT Tools from Google (Tor Jeremiassen, Yenkai Wang)
- 12:45 — SVM: Synthesizable Approach to Efficient RISC-V CPU Verification (Yinan Xu)
Why RISC-V Is Uniquely Positioned for AI
Krste’s core argument: among competing ISAs, only RISC-V works well for all three AI roles:
- AI Host ISA — e.g., Nvidia port of CUDA stack to RISC-V
- AI Device ISA — e.g., many AI accelerators already based on RISC-V
- Self-hosted AI ISA — e.g., edge AI, plus upcoming agentic CPUs
RISC-V ISA scales down to MMU-less embedded devices while keeping the same vector and matrix extensions. It supports AI innovation and differentiation through custom extensions while sharing standard compute kernel and software stack costs across all possible AI compute environments.
He referenced Myer and Sutherland’s 1968 paper “On the Design of Display Processors” — the Wheel of Reincarnation concept — arguing that the CPU/GPU host/device split is history repeating itself, and RISC-V’s self-hosted model breaks the cycle.
RISC-V DSP Extensions
The RISC-V P extension (DSP) is now stable on path to ratification after long development:
- Packed integer/fixed-point (8b/16b/32b/64b) operations on integer x registers
- Over 100 new instructions
- Upcoming: Vector DSP extension TG initiated — DSP instructions on vector registers, candidate new instructions for greater fixed-point support, permutations for FFTs, complex arithmetic
RISC-V New Security Extensions
A comprehensive security roadmap:
- SPMP — S-mode RTOS/supervisor protection from U-mode tasks
- RISC-V Worlds — secure global partitioning of devices on SoCs
- IOPMP — embedded device security
- Supervisor Domains — flexible confidential computing support
- CHERI — new base ISAs (RV32Y/RV64Y) bringing capability-based security
- Lightweight Memory Tagging — memory safety via pointer-masking
- Additional Crypto — PQC and other vector crypto enhancements
Standardizing Microcontrollers
Krste argued that while many microcontroller use cases benefit from extreme specialization, automotive and richer embedded software stacks would benefit from standard profiles. The RVM ISA profile mandates fast interrupts, standard nested protection (sPMP), security features (RISC-V Worlds), and debug/trace support. “Pieces mostly exist now, but need to keep working on common specs to drive ecosystem forward.”
Long Instructions (greater than 32b)
RISC-V included variable-length instructions from the beginning — compressed 16b instructions save code-size. Krste emphasized this was designed for long-term success: the ISA will not disappear due to owner changing business model or folding. Fixed 32b instruction formats in other ISAs are already running out of encoding room, becoming a barrier to long-term evolution. Longer instructions (greater than 32b) also help reduce code size, improve performance, and support the ever-growing number of new operators and datatypes.
Keynote Summary: “RISC-V Is Inevitable”
Krste closed with a powerful summary:
- Milestone: 2026 sees multiple high-performance RVA23 systems delivered — server ecosystem can now start to evolve rapidly
- RISC-V uniquely positioned to create portable open-standard AI platforms at all scales
- “RISC-V is inevitable”
Keynotes and Highlights
XiangShan: Top-Performing Open-Source RISC-V CPU
The XiangShan team presented their open-source high-performance RISC-V CPU that is closing the gap with ARM — the performance trajectory from YQH through M21 to KMH v1/v2/v3 shows RISC-V approaching x86/ARM levels by 2027-2028. The “iceberg” metaphor highlights the massive agile development infrastructure beneath: Chisel RTL, NEMU reference model, GoldenStar multi-core memory model, DiffTest co-simulation, and full CI pipeline with FPGA emulation.
Verification Infrastructure: Co-Simulating DUT and REF
With the RVA23 profile’s complexity (integer, float, vector, hypervisor, debug CSRs, plus memory consistency and TLBs), extensive simulation before tape-out is critical. The approach co-simulates RTL (Verilog) against a software reference model (C++), comparing instruction commits — match means no-bug, mismatch flags a bug.
True Random Number Generators (TRNG)
The VASCO#3 project validates entropy source models on silicon for RISC-V security. New entropy sources proposed (ERO, MURO, COSO) with jitter analysis confirmed aligned with pre-silicon simulations, and flicker/thermal noise coefficients matching expectations — critical for PQC-ready RISC-V implementations.
DeepComputing: Turning RISC-V Into Reality
Great meeting the DeepComputing team — they are making RISC-V tangible with actual consumer hardware including the DC-ROMA Mini PC (raffle giveaway at the summit!). Their Meridian RDC and RXV products bring RISC-V to developers who want to run real workloads today.
Performance Profiling Tools
Impressive demo of RISC-V performance profiling tools showing timeline reports with IPC, function call stacks, bank conflicts, branch mispredicts, and memory activity across multi-threaded workloads (bzip2 1T/2T/4T on i8500 CPU model). This kind of tooling maturity is what makes RISC-V production-ready.
In the Auditorium
The sessions covered deep processor microarchitecture — from renamed instruction streams and dispatch logic to out-of-order execution pipelines. Professor Roberto Giorgi from Università degli Studi di Siena walked through cycle-by-cycle pipeline execution examples.
Meeting Brian Harrington (Red Hat)
Great to connect with Brian Harrington from Red Hat — a speaker at the summit with the best badge ribbons: “Software Therapist” and “Kubernetes.” The intersection of RISC-V and cloud-native is getting real.
Bologna
Beautiful city — even with construction everywhere.
Deep-Dive: RISC-V Processor Microarchitecture
The tutorial sessions by Roberto Giorgi (Università degli Studi di Siena) were a masterclass in out-of-order processor internals on RISC-V.
Pipeline Simulation and Stall Analysis
Live demonstration of a RISC-V out-of-order pipeline simulator — showing instruction flow through fetch, dispatch, issue, and completion stages. The tool visualizes pipeline stalls (no slots available, data hazards) and physical register allocation in real-time.
Physical Register Management
Key insight on register reclamation:
- A physical register can be freed once the last read has been completed
- With precise exceptions: freed after the corresponding logical register has been updated
- The Pi,old field in the ROB indicates when a physical register can be freed (after commit)
Dispatch and Reorder Buffer Detail
Cycle-by-cycle walkthrough showing how instructions are dispatched into the instruction window, renamed via the register map, and tracked in the Reorder Buffer (ROB) — fundamental concepts for anyone designing RISC-V out-of-order cores.
”One Student One Chip” Initiative — BOSC
Xiaoke Su from the Beijing Institute of Open Source Chip (BOSC) presented the “One Student One Chip” initiative — a MOOC-based program teaching students to build RISC-V chips from scratch.
The OSOC (Open Source SoC) course design is remarkable:
- No limitations on university, major, grade, or background
- Full-stack training from Application → Runtime → OS → ISA → Micro-architecture → Circuit → Synthesis → Physical design → GDSII
- Software track: GCC, LLVM, U-boot, OpenSBI, QEMU, Linux
- Chip track: XiangShan, cache, coherency, OoO, branch prediction
- EDA track: Place, route, timing analysis, clock tree, floorplan
- Goal: education equality → full-stack training → enter community or company
Wednesday Morning Plenary Schedule
The Wednesday morning plenary packed heavy hitters:
| Time | Talk | Speaker |
|---|---|---|
| 9:00 | RISC-V State of the Union | Krste Asanovic |
| 9:30 | Nuclei: Full-Spectrum RISC-V IP and Automated SoC Design from Months to Hours | Bob Hu |
| 9:45 | ARBEL: The Leading Server-Class RISC-V CPU | Yiftach Gilad |
| 10:00 | RISC-V: Enabling Open Physical AI | Luca Benini |
| 11:30 | From Eyewear to Silicon: RISC-V for Low-Power AI in Next-Gen Smart Glasses | Marco Fariselli |
| 12:00 | RVEdge-Vision: Fully Open, Ultra-Efficient On-Device AI Platform for Smart Eyewear | Michele Magno |
| 12:15 | RIVIERA: A Programmable RISC-V Edge Architecture for NFC Signal Processing | Luca Lingardo |
| 12:30 | Accelerating RISC-V Innovation with open MPACT Tools from Google | Tor Jeremiassen, Yenkai Wang |
| 12:45 | SVM: A Synthesizable Approach to Efficient RISC-V CPU Verification | Yinan Xu |
The Main Auditorium
RISC-V International: Learn at learn@riscv.org
A representative from RISC-V International took the podium to highlight education initiatives. For anyone interested in RISC-V learning programs and academic collaborations: learn@riscv.org.
RISC-V State of the Union — Krste Asanović (SiFive)
RISC-V’s Chief Architect delivered the opening keynote covering adoption across computing markets — from embedded to AI. Key announcements:
- Security extensions — new ISA additions for hardware-enforced isolation
- Matrix extensions for AI — standardized acceleration for ML workloads
- New profile and platform initiatives — enabling portable software across vendors
Krste co-founded RISC-V at UC Berkeley in 2010 and the RISC-V Foundation in 2015. Seeing the ISA mature from academic project to industry standard with billions of cores shipped is remarkable.
RISC-V: Enabling Open Physical AI — Luca Benini (ETH Zurich / University of Bologna)
Professor Benini made a compelling case for RISC-V in Physical AI — autonomous systems (robots, cars, satellites) where energy efficiency, safety, and robustness are non-negotiable:
- Deep domain specialization across all levels of the chip design hierarchy
- Domain-specific design automation tools enabled by the open ISA
- Addressing reliability concerns in advanced IC technology
- The strategic importance of an open-platform approach for safe, reliable Physical AI
Developing an Open Agentic SoC — Tanya Dadasheva (Ainekko)
One of the most forward-looking talks: hardware defined by models, not the other way around.
Ainekko’s approach:
- Many-core RISC-V architecture with tile-based compute and memory
- Automated model-to-hardware mapping at packaging time
- 1,088-core tape-out validated, scaling to 4,000+ cores
- Open-sourced through OpenHW Foundation (CORE-ET project) and AIFoundry
- Sits between FPGA flexibility and ASIC efficiency
The key insight: models define the hardware — eliminating per-model tape-outs while maintaining high performance.
Beyond Privilege: The RISC-V Isolation Toolbox — Andrew Dellow (Qualcomm)
A deep-dive into RISC-V’s security isolation mechanisms spanning the full spectrum:
| Mechanism | Use Case |
|---|---|
| PMP/ePMP | Physical memory protection (MCUs) |
| SPMP | Supervisor physical memory protection |
| Privilege levels | Execution control |
| Virtualization | Hypervisor extensions |
| RISC-V Worlds | Hardware-enforced compartmentalization |
| Supervisor Domains | Fine-grained isolation within S-mode |
The future is composable isolation — layering mechanisms for mixed-criticality systems, safety-certified platforms, and confidential computing.
From Eyewear to Silicon: RISC-V for Low-Power AI — Marco Fariselli (Luxottica)
Luxottica (Ray-Ban, Oakley) is using RISC-V for next-generation smart glasses:
- Speech enhancement in noisy environments
- Eye tracking for interaction and health monitoring
- Automatic speech recognition for hands-free control
- All running simultaneously within tens of milliwatts
Why RISC-V? Custom ISA extensions for emerging ML operators without full hardware redesign. The open ecosystem lowers the barrier to custom silicon for teams whose core expertise is outside traditional semiconductor IP.
RISC-V Innovation at Scale — Andrea Gallo (CEO, RISC-V International)
The CEO’s overview of ecosystem momentum:
- RVA23 profile ratified — enabling portable software binaries
- Real-world deployments across automotive, embedded, AI, and data center
- Hardware and software enablement from across the ecosystem
Matrix Extensions: Delivering on the Promise — Philipp Tomsich (VRULL)
The matrix extension family is converging — two of four extensions approaching spec freeze:
- IME (Integrated Matrix Extensions) — lightweight, reuses RVV state
- VME (Vector Matrix Extensions) — dedicated accumulator registers
- Unified LLVM-MLIR lowering path targeting both extensions
- Algebraic tile geometry scaling naturally with VLEN
RISC-V matrix support is no longer a roadmap item — it is arriving.
Server Platform 1.0: One Spec to Boot Them All — Radim Krčmář (Qualcomm)
The RISC-V Server Platform Specification defines a clear baseline for high-performance platforms:
- Composing RVA23 profile + UEFI/ACPI boot + SBI interfaces
- Secure boot, attestation, and BMC-based management
- One portable binary for OS and hypervisor developers
- Reducing fragmentation across deployment environments
Albania as an AI Factory — Kushtrim Shala (Digital Valley Albania)
A visionary talk on how a small country can leapfrog into sovereign AI infrastructure:
- RISC-V-native AI compute facility for the Western Balkans
- Embedding RISC-V into Albanian CS education
- European Digital Innovation Hub (EDIH) under Digital Europe Programme
- Open ISA as a strategic instrument of digital sovereignty
RISC-V for the Planet — Marcelo Zuffo (USP)
The Internet of Trees project: deploying RISC-V-based smart probes in forest environments for real-time environmental intelligence. Open silicon enabling:
- Ultra-low-power edge AI in remote environments
- Secure communication and trusted operation
- Scalable integration with cloud platforms
- Planetary monitoring infrastructure
The European RISC-V Ecosystem
The sponsor list tells the story of RISC-V’s European strength:
Platinum: BOSC, E4 Computing, MIPS, Nuclei System Gold: CEA, Epic Semi, NextSilicon, Qualcomm, SiFive, Tenstorrent Silver: Axelera, Barcelona Supercomputing Center, Infineon, lowRISC, Microchip, OpenHW Foundation, PULP Platform
The combination of academic research (ETH Zurich, BSC, Bologna) and industry (Qualcomm, Infineon, Luxottica) is what makes RISC-V in Europe uniquely powerful.
Key Takeaways
- AI is the killer app — matrix extensions, agentic SoCs, physical AI all point to RISC-V as the open foundation for AI silicon
- Security is first-class — isolation toolbox from MCUs to confidential computing
- Server Platform 1.0 — RISC-V is ready for data center workloads
- European sovereignty — open ISA as strategic infrastructure, not just technology
- Edge AI — smart glasses, environmental monitoring, automotive — all powered by customizable RISC-V cores
What This Means for Enterprise AI
For organizations building AI infrastructure:
- Custom silicon without vendor lock-in — RISC-V enables domain-specific accelerators
- Confidential computing — hardware-enforced isolation for regulated AI workloads
- Edge deployment — milliwatt-level AI inference on custom RISC-V cores
- Software portability — RVA23 profile + Server Platform = write once, run anywhere
The future of computing is open, and Bologna just showed us what that looks like.
