The RISC-V Summit Europe 2026 took place June 8-12 at Palazzo dei Congressi in Bologna, Italy — and it was incredible to witness how far the open-source silicon ecosystem has come. From server-grade CPUs to edge AI accelerators, from academic research to production-ready cloud infrastructure, the RISC-V ecosystem is no longer “up and coming” — it’s arrived.
The Expo Floor
The exhibition hall was buzzing with energy. Booths from MIPS (now a GlobalFoundries company), Epic Semi, ESWIN, Lauterbach, and dozens more showcased the breadth of the RISC-V ecosystem.
ESWIN: RV23-Based Server CPUs
One of the highlights was visiting the ESWIN booth (Beijing Eswin Computing Technology Co., Ltd.). They’re positioning themselves as a RISC-V oriented chip product provider with serious credentials: 1,660+ patent applications, 110+ global customers, and products spanning smart home, automotive, industry, and embodied intelligence.
Their RV23-based RISC-V server CPU is explicitly built for:
- AI Factories
- Cloud infrastructure
- Sovereign AI
This is significant — RISC-V is now targeting the same datacenter workloads that x86 and Arm dominate.
Scaleway EM-RV1: First RISC-V Cloud Server
Scaleway showcased the EM-RV1 — the first RISC-V server available in the cloud. The hardware is impressive: 7 compute modules based on the THead TH1520 SoC, each with 16GB RAM and 128GB storage.
This isn’t a prototype — it’s production infrastructure you can rent today. RISC-V in the cloud is real.
Tenstorrent Blackhole p150a
Tenstorrent had their Blackhole p150a on display — a Tensix processor in an active-cooled PCIe form factor:
- 120 Tensix cores
- 16 big RISC-V cores
- Up to 32GB GDDR6 memory
- 664 TeraFLOPS (BLOCKFP8)
The distinctive zebra-stripe design is unmistakable. This is Jim Keller’s vision of RISC-V AI acceleration becoming reality.
Developer Board Showcase
The developer board table was packed — dozens of RISC-V development boards from various manufacturers showing the ecosystem breadth from tiny MCUs to Linux-capable SBCs.
One Student One Chip
A fantastic educational initiative: “One Student One Chip” featured StarrySky Boards from Seasons 3 and 4, manufactured by JLC Technology Group. Teaching the next generation of chip designers on actual silicon.
A Journey of Talent and Inspiration
The summit honored the women who shaped microelectronics and semiconductors — from Ada Lovelace and Grace Hopper to Hedy Lamar and modern pioneers. A beautiful reminder of the shoulders we stand on.
Sponsors and Ecosystem
The sponsor wall tells the story of RISC-V’s momentum:
Platinum: BOSC, E4 Computer Engineering, MIPS, Nuclei
Gold: Breker, CEA, Epic Semi, ESWIN, NextSilicon, Qualcomm, SiFive, Tenstorrent, Tristan (Solde), Xuantie
Silver: Akeana, Andes, Arteris IP, Axelera, Barcelona Supercomputing Center, baya Systems, Bosch, Chips-IT, CINECA, CircuitSutra, DeepComputing, ERGtech, GLIWA, Infineon, InspireSemi, Lauterbach, lowRISC, Microchip, OmniTrust, OpenHW, PlanV, PULP, Real Intent, RIOS, RISE, SEGGER, SpaceMIT, Tera Pines
Poster Session: Academic Research
The poster session was outstanding — packed with researchers presenting cutting-edge RISC-V work.
Monte Cimone v3: RISC-V in HPC
The Monte Cimone v3 cluster from University of Bologna, E4, CINECA, and ETH Zurich demonstrated where RISC-V stands in high-performance computing:
- Based on the new SG2044 platform implementing RVV 1.0
- MCv3 more than doubles single-core performance vs MCv2
- 139x speedup over MCv1 with 10x energy efficiency improvement
- At 16 cores peak efficiency: achieves 91% of NVIDIA and 46% of Intel normalized performance
- Reaches 68% and 80% of their energy efficiency respectively
The cluster topology uses SLURM with two SG2044 single-socket nodes and four SG2042 dual-socket nodes.
GLIWA: RISC-V vs ARM in Real-Time Systems
Christian Wenzel-Benner from GLIWA GmbH presented a fascinating synchronized T1-based comparison between Hazard3 and Cortex-M33 cores on the RP2350 / Pi Pico2 dual-architecture platform. Same memory, same peripherals, same clock — just different ISAs.
Key findings: Hazard3 (RISC-V) performs competitively with Cortex-M33 across RAM copy, integer operations, and floating point, with some benchmarks favoring each architecture.
CVA6 Optimization (PlanV / OpenHW)
The CVA6 Optimization poster from PlanV GmbH showed how adding a re-order buffer (ROB) and registering controller outputs (COR) achieves a 14% increase in operating frequency while maintaining the same CoreMark/MHz performance.
Sail Model for Chip Verification
Researchers from the Chinese Academy of Sciences presented an efficient approach to apply the RISC-V Sail Model to chip verification. Their methodology using Pydrofoil achieved integration with the XiangShan processor in only ~800 lines of Python code.
openEuler for RVA23
The openEuler team presented their work building a RISC-V server OS with ecosystem partners:
- openEuler 24.03 LTS SP3 is the first LTS with RVA23 support
- Toolchain: GCC 14.3, Binutils 2.42, LLVM 20
- RVCK (RISC-V Common Kernel) provides shared platform support
- XiangShan pre-silicon validation on FPGA platforms
- Roadmap targeting RVA23 and RISC-V Server Platform Specification in 2026
ETH Zurich: Open-Source SD-Card Host Controller
The PULP team at ETH Zurich presented an open-source SDHCI controller for Linux-capable RISC-V SoCs:
- Reaches 11.1 MB/s (8x SPI throughput)
- Skipping fences yields 24.9x read and 11.3x write improvement
- Compact: 16 kGE vs 86 kGE for SPI (5.4x less)
- Open-source SDHCI v1.0 RTL releasing summer 2026
Functional Safety with Formal Assurance (FZI)
The FZI team demonstrated automated DMR (Dual Modular Redundancy) hardening via a CIRCT compiler pass — generating safety-critical hardware designs with formal verification at no performance cost.
SMSIC: Software-Interrupt MSI Controller (Xuantie/Alibaba)
Alibaba’s Damo Academy (Xuantie) presented SMSIC — an AIA extension that decouples IPI from the MSIC, enabling massive vCPU scaling for VM-based secure containers in the AI Agent era.
1W Envelope: Edge AI on RISC-V Systolic Arrays
Daniel Klunder from DHBW Stuttgart explored area-energy trade-offs of scalable RISC-V systolic arrays in Sky130. Key insight: 16x16 mesh is the “sweet spot” (63.9% utilization) — going to 32x32 causes a performance collapse due to padding waste.
RISC-V SoCs for Space Communications
ETH Zurich and Celeste Technologies presented next-generation RISC-V SoCs for non-terrestrial network gNB processors — software-defined, low power, meeting 1ms latency at 600Mbps. A single RV64GC core is ~270x slower than real-time, making ISA-specialization and RVV mandatory.
Mixed-Criticality on RISC-V (University of L’Aquila)
A lightweight multi-context architecture for safety-critical systems — proposing a hardware extension to the RISC-V ISA for running mixed-criticality workloads with minimal timing overhead.
Runtime Decoder Reconfiguration (TU Graz)
TU Graz demonstrated FPGA-based partial runtime reconfiguration for dynamically switching between compact and stricter decoder variants in minimal-area RISC-V cores — security meets efficiency.
XiangShan DiffTest-H: Hardware-Accelerated CPU Verification
One of the standout technical talks covered DiffTest-H — a hardware-accelerated co-simulation framework for verifying the XiangShan processor, the top-performing open-source RISC-V CPU.
The problem is clear: traditional software simulators are painfully slow. VCS simulates a single-core XiangShan CPU at under 100 cycles per second. Verilator/GSIM manage thousands. Cadence Palladium reaches MHz speeds but costs millions. FPGAs are fast (tens of MHz) but lack observability.
DiffTest-H solves this by combining FPGA speed with instruction-level debugging:
- 13.8 MHz@FPGA for XiangShan — 2,300x faster than Verilator
- Only 3.2% LUT area overhead on Xilinx VU19P
- 151 bugs uncovered in XiangShan through co-simulation
- Hardware packing and fusion reduce HW/SW communication bandwidth
- Error-replay maintains full debuggability despite data fusion
The key innovation: nearly 15 verification events generate 1.2KB per cycle (60 GB/s@50MHz). DiffTest-H uses structure-wise packing and order-decoupling fusion to aggregate scattered events into efficient packets, with load smoothing to minimize FPGA area.
The framework is open-source at github.com/OpenXiangShan/difftest and supports XiangShan, NutShell, and Rocket cores across VCS, Verilator, GSIM, Cadence Palladium, and Xilinx FPGAs.
Keynote Stage
The main stage keynote sessions featured presentations from RISC-V International leadership, setting the vision for the ecosystem’s next phase.
Meeting the RISC-V International Team
Great meeting Megan Lehn from RISC-V International — the staff who make events like this happen.
Key Takeaways
- RISC-V servers are production-ready — Scaleway’s EM-RV1 and ESWIN’s RV23 CPUs prove it
- HPC is achievable — Monte Cimone v3 reaches 91% of NVIDIA Grace performance at comparable energy efficiency
- AI acceleration is here — Tenstorrent’s 664 TFLOPS Blackhole is a serious contender
- The ecosystem is deep — 50+ sponsors, hundreds of academic papers, production deployments
- European sovereignty — many presentations explicitly target digital sovereignty, with EU-funded projects and local manufacturing
The RISC-V Summit Europe continues to demonstrate that open-source silicon is not just a research curiosity — it’s the foundation of future computing infrastructure.
RISC-V Summit Europe 2026 took place June 8-12 at Palazzo dei Congressi, Bologna, Italy.
