Space is the most unforgiving environment electronics can face — bathed in radiation, impossible to repair, and expected to work flawlessly for decades. So it is a striking endorsement that space agencies and satellite makers are increasingly choosing RISC-V. The headline: NASA selected a RISC-V design for its next-generation spaceflight computer. Here is why the open ISA is heading off-world.
Why Space Computing Is Special
Spacecraft electronics face constraints unlike anything on the ground:
- Radiation — cosmic rays and charged particles flip bits (single-event upsets) and cause permanent damage.
- No repairs — once launched, hardware must self-detect and recover from faults autonomously.
- Extreme longevity — missions run for 10–20+ years, so the architecture and software must remain supportable for decades.
- Tight power and thermal budgets — every watt counts on a satellite.
Traditionally these needs were met with expensive, proprietary, and often technologically dated radiation-hardened processors. RISC-V offers a fresh path.
NASA’s HPSC: The Landmark Win
The flagship example is NASA’s High-Performance Spaceflight Computing (HPSC) processor. NASA selected a RISC-V-based design, developed with SiFive and Microchip, to be the workhorse compute platform for future missions. The goal is a leap in onboard processing power — for autonomous navigation, on-board AI, and data handling — over the decades-old chips that still fly today.
That a risk-averse agency like NASA chose RISC-V for mission-critical compute is a powerful signal of the ISA’s maturity and the strength of its ecosystem.
Why RISC-V Fits Space So Well
The same qualities that win in automotive and sovereignty apply, amplified:
- Customization — designers can add fault-tolerance features (redundancy, error detection) directly into an open core, rather than accepting whatever a vendor offers.
- No single-source / export risk — space programs are wary of proprietary, export-restricted IP from a single supplier; an open ISA with multiple implementers reduces that risk (a clear sovereignty benefit for national programs).
- Architectural stability — RISC-V’s frozen base ISA protects software investments across multi-decade missions.
- Auditability — for the highest-assurance systems, being able to inspect the core design itself is invaluable.
Radiation Hardening and Fault Tolerance
An open ISA does not magically survive radiation — that is an implementation property, achieved with established techniques layered onto a RISC-V core:
- Lockstep / redundant cores — run computations in duplicate (or triplicate) and vote on results to catch faults, building on the same mechanisms used for functional safety.
- ECC everywhere — error-correcting codes on memories and buses to catch and fix bit flips.
- Triple-modular redundancy (TMR) — critical logic replicated three times with majority voting.
- Rad-hard processes — special manufacturing to resist permanent damage.
- Watchdogs and scrubbing — continuously check and refresh memory to prevent accumulated errors.
Because RISC-V cores are open and customizable, these protections can be designed into the silicon precisely where a mission needs them.
NewSpace and Small Satellites
It is not only flagship agency missions. The NewSpace boom — constellations of small, cheaper satellites — is a natural fit for RISC-V’s low cost and flexibility. CubeSats and smallsats can use commercial RISC-V parts with mission-appropriate fault tolerance, getting capable compute without the price tag of traditional rad-hard chips. The same embedded strengths that win on Earth apply in orbit.
On-Board AI in Orbit
A growing driver is edge AI in space: processing imagery and sensor data on the satellite instead of downlinking everything. That demands far more compute than legacy space processors provide — exactly the gap HPSC and RISC-V AI acceleration aim to fill. Smarter satellites that decide what data is worth sending home need powerful, efficient, customizable silicon.
The Bottom Line
Space is the ultimate proving ground, and RISC-V is rising to it. NASA’s HPSC processor — RISC-V-based, built with SiFive and Microchip — is the landmark, but the logic applies across the industry: an open, customizable, stable ISA lets designers build in the radiation hardening and fault tolerance that missions demand, free of single-source and export risk, with software supportable for decades. From flagship probes to NewSpace constellations doing AI in orbit, open silicon is going to space.
Part of my RISC-V series. See also automotive & functional safety and European digital sovereignty.
