RISC-V’s modularity is its superpower — and its biggest risk. With dozens of optional extensions, what stops the ecosystem from fragmenting into incompatible chips that no single OS can target? The answer is profiles, and in 2026 the one that matters most is RVA23. This post explains both.
The Fragmentation Problem
Imagine two RISC-V chips. One implements RV64GC. Another adds vectors but skips an extension the first had. A third reorders the mix. Each is a valid RISC-V processor — but a Linux distribution cannot ship one binary that runs optimally on all of them. Either it targets the lowest common denominator (wasting capability) or it builds many variants (a maintenance nightmare).
This is the classic tension of any flexible platform. RISC-V’s solution is to define agreed-upon bundles.
What a Profile Is
A profile is a named, versioned set of mandatory (and some optional) extensions that:
- Hardware commits to implementing, and
- Software is allowed to assume.
It is a contract. If a chip claims RVA23 compliance, an OS built for RVA23 will run on it. That single guarantee is what turns “infinite modularity” into “portable software.”
Profiles come in families:
- RVA — application processors (the Linux-class chips).
- RVB — a related application-class series.
- RVM — microcontroller / embedded profiles for bare-metal use.
The Profile Timeline
- RVA20 — the first application profile, roughly equivalent to a standardized
RV64GCbaseline. - RVA22 — added more mandated extensions (various Z-extensions, improved baseline), but left vectors optional.
- RVA23 — ratified in 2024, the current flagship. It makes the big two mandatory.
What RVA23 Changes
RVA23 is a turning point because it mandates what previous profiles left optional:
- V (Vector, RVV 1.0) is now required. Every RVA23 chip can run vector code, so distributions can build vectorized libraries (math, crypto, AI) and trust they will run everywhere.
- H (Hypervisor) is now required. Virtualization — and by extension cloud and confidential computing — is guaranteed.
- A defined set of Z-extensions (bit-manip, scalar crypto, cache management, and more) rounds out a genuinely capable baseline.
The practical upshot: an ISV can build one RVA23 binary and ship it across compliant application processors, exactly as they do for x86-64 or ARM64 today. That is the missing ingredient for a thriving software ecosystem.
The Server Platform Specification
Profiles define the ISA contract. Servers need more — a platform contract covering firmware, boot, and discovery. That is the RISC-V Server Platform Specification, which composes:
- RVA23 as the ISA baseline
- Server-class SoC requirements
- UEFI/ACPI boot (via the Boot and Runtime Services, BRS)
- SBI interfaces
- Security foundations: roots of trust, secure boot, attestation, BMC-based management
Together these let an OS or hypervisor target a single portable binary across server hardware — “one spec to boot them all,” as one Summit talk put it. This is the connective tissue behind RISC-V in the datacenter.
How OSes Use Profiles
- openEuler shipped its first LTS with RVA23 support and is building a RISC-V server OS around it (with RVCK, the RISC-V Common Kernel, for shared platform support).
- Debian, Ubuntu, and Fedora RISC-V ports increasingly target a modern profile baseline.
- Toolchains expose profiles via
-marchstrings, so you can compile to the profile rather than to one specific chip.
Checking and Targeting a Profile
On hardware, the active extensions show up in /proc/cpuinfo:
cat /proc/cpuinfo | grep isa
# isa : rv64imafdcv_zicsr_zifencei_zba_zbb_..._hWhen compiling, target the capabilities you rely on (see Build a RISC-V Toolchain):
# Roughly an RVA23-class target with vectors
riscv64-linux-gnu-gcc -march=rv64gcv -mabi=lp64d app.c -o appYou can validate portability in QEMU by toggling extensions on the emulated CPU and confirming your binary still runs.
Why This Is the Most Important Work in RISC-V
It is tempting to find profiles less exciting than a 64-core chip or an AI accelerator. But profiles are what make all that silicon usable at scale. Without RVA23, every interesting RISC-V chip would be a software island. With it, the whole ecosystem compounds — more chips targeting the same baseline, more software targeting that baseline, a flywheel that finally rivals the portability of x86 and ARM.
The Bottom Line
Profiles are RISC-V’s answer to its own flexibility, and RVA23 is the profile that made application-class RISC-V truly portable by mandating vectors and virtualization. Combined with the Server Platform Specification, it gives software a stable target from edge to datacenter. If you remember one acronym from the RISC-V software story of 2026, make it RVA23.
Part of my RISC-V series — see RISC-V Extensions Explained and The RISC-V Ecosystem in 2026.
