The RISC-V ISA being open is only half the story. The other half is that you can also get the implementations — real, synthesizable processor designs — as open source. At RISC-V Summit Europe 2026, open-source cores were everywhere, from teaching tools to a superscalar CPU competitive with commercial silicon. Here is a tour of the most important ones.
Why Open Cores Matter
An open ISA defines what instructions a chip understands. But the microarchitecture — the pipeline, caches, branch predictor, and execution units — is where the engineering value and the secrets usually live, and it is normally proprietary.
Open-source cores change that. They make the implementation itself inspectable and reusable, which unlocks:
- Education — students learn on real, industrial-grade designs (the basis of One Student One Chip).
- Security — researchers can audit the actual hardware, not just the spec (RISC-V security).
- Research — new ideas can be prototyped on a shared, modifiable baseline.
- Custom silicon — startups and labs can build royalty-free SoCs without designing a CPU from scratch.
This is “open silicon all the way down,” and it is central to digital sovereignty.
XiangShan: The Open-Source Flagship
XiangShan (香山) is the standout. Developed by the Beijing Institute of Open Source Chip (BOSC) and the Chinese Academy of Sciences, it is a superscalar, out-of-order RISC-V core — and widely considered the highest-performing open-source CPU in existence. It is not a teaching toy; it targets performance competitive with commercial application processors.
XiangShan also drove one of the most interesting verification stories at the Summit: DiffTest-H, a hardware-accelerated co-simulation framework that reached 13.8 MHz on FPGA (around 2,300× faster than Verilator) with only ~3.2% area overhead, and uncovered 151 bugs in XiangShan through co-simulation. That tooling — open-source at github.com/OpenXiangShan/difftest and supporting XiangShan, NutShell, and Rocket — shows the open ecosystem building serious verification infrastructure, not just RTL.
CVA6 (Ariane): The Application-Class Workhorse
CVA6, formerly Ariane, is a 64-bit, in-order, application-class core that originated at ETH Zurich and is now stewarded by the OpenHW Group. It can boot Linux, is well documented, and has become the default starting point for countless research SoCs and custom designs.
At the Summit, PlanV presented a CVA6 optimization adding a re-order buffer and registering controller outputs to achieve a 14% frequency increase at the same CoreMark/MHz — a concrete example of the community improving a shared, open design that everyone benefits from.
lowRISC and Ibex: Security-Focused
lowRISC (a UK non-profit) produces Ibex, a small, well-verified 32-bit core popular in embedded and security work, and is a key contributor to OpenTitan — an open-source silicon root of trust. If your interest is embedded or hardware security, Ibex is a friendly, production-quality entry point.
The PULP Platform: Research Powerhouse
The PULP (Parallel Ultra-Low-Power) platform, a collaboration between ETH Zurich and the University of Bologna, is one of the most influential open-hardware efforts anywhere. It spans:
- Tiny cores (Zero-riscy, Ibex lineage) for ultra-low-power
- Larger cores and clusters for parallel compute
- The research feeding the Monte Cimone HPC clusters and countless edge-AI designs
PULP’s body of validated, ultra-low-power microarchitecture IP dramatically lowers the barrier to building custom silicon — a recurring theme in the edge-AI talks.
Rocket and BOOM: The Berkeley Lineage
From RISC-V’s birthplace at UC Berkeley come Rocket (an in-order core) and BOOM (the Berkeley Out-of-Order Machine), generated via the Chipyard SoC framework in Chisel. They remain widely used in academia and are a superb way to learn modern SoC design with a productive hardware-construction language.
A Quick Comparison
| Core | Origin / Steward | Class | Best for |
|---|---|---|---|
| XiangShan | BOSC / CAS | Superscalar OoO 64-bit | High performance, research |
| CVA6 (Ariane) | ETH Zurich / OpenHW | In-order 64-bit, Linux | SoC baseline, education |
| Ibex | lowRISC | Small 32-bit | Embedded, security, OpenTitan |
| Rocket / BOOM | UC Berkeley | In-order / OoO | Academia, Chisel SoC design |
| PULP cores | ETH Zurich / UniBo | Ultra-low-power → cluster | Edge AI, HPC research |
Getting Hands-On
You do not need a fab to explore these. Most open cores can be:
- Simulated with Verilator or QEMU for functional testing
- Synthesized onto an FPGA to run real (if slower) hardware
- Modified — change the pipeline, add an instruction, and re-run the test suite
For learning, CVA6 or a Chipyard/Rocket setup is the most approachable; for performance research, XiangShan is the frontier.
The Bottom Line
Open-source cores are what make RISC-V genuinely open — not just a free spec, but free implementations you can read, run, modify, and ship. From XiangShan’s commercial-class performance to CVA6’s Linux-capable accessibility to PULP’s ultra-low-power research, there is an open core for every need. That depth of openness is unique in the processor world, and it is a big part of why RISC-V’s ecosystem compounds so fast.
Part of my RISC-V series. See also What Is RISC-V? and the Summit highlights.
