Floating-point is where a lot of real computing happens — graphics, signal processing, scientific code, and machine learning all lean on it. RISC-V handles it with the same philosophy it brings to everything else: a small mandatory base plus optional, composable extensions you add only when you need them. Here is how RISC-V floating-point fits together.
Floating-Point as an Extension
In the RISC-V world, even floating-point is optional. The base integer ISA has no FP at all — perfect for a tiny controller that never needs it. When you do need real numbers, you add one or more floating-point extensions. This keeps small cores small while letting bigger chips scale up, which is exactly the modularity that makes RISC-V so adaptable.
The Precision Ladder: F, D, Q
The core FP extensions are named by precision, each building on the last:
| Extension | Precision | Width |
|---|---|---|
| F | Single | 32-bit |
| D | Double | 64-bit |
| Q | Quad | 128-bit |
All follow the IEEE 754 standard, so results match what you would expect on other platforms. The common G shorthand (as in RV64GC) bundles the general-purpose set, which includes both F and D — the combination most application software assumes.
The f Registers and Rounding Modes
When a core implements F/D/Q, it gains a separate bank of 32 floating-point registers (f0–f31), distinct from the integer file. Floating-point arguments travel in these registers (fa0–fa7) under a hard-float ABI. RISC-V also exposes the IEEE rounding modes (round-to-nearest, toward zero, up, down) via a control register and per-instruction fields, plus exception flags for inexact, overflow, and invalid operations — everything numerical code needs to be correct and reproducible.
# double add: fa0 = fa0 + fa1
fadd.d fa0, fa0, fa1Hard-Float vs Soft-Float
What if a core has no FP hardware? Code still compiles — the compiler emits soft-float library routines that emulate floating-point with integer instructions. It is slower, but it runs anywhere. With FP hardware present, you use hard-float and operations execute natively. This choice is baked into the ABI (for example lp64d selects LP64 with double-precision hard-float), so all linked objects must agree.
Lightweight Options: Zfh and Zfinx
RISC-V keeps adding smaller options for cost-sensitive designs:
- Zfh — half-precision (16-bit) FP. Half precision is a workhorse of AI inference and graphics, where full precision is wasted.
- Zfinx — puts floating-point values in the integer registers, eliminating the separate
fregister file to save silicon area on tiny cores.
These reflect RISC-V’s habit of offering exactly the right amount of capability for a given budget rather than forcing one heavy standard on everyone.
Beyond Scalar: Vectors
For throughput-heavy numerical work, scalar FP gives way to the Vector extension (RVV), which applies floating-point operations across whole arrays at once — the foundation for high-performance and HPC workloads on RISC-V.
The Bottom Line
RISC-V treats floating-point the way it treats everything: modular and optional. Add F, D, or Q for single, double, or quad precision; reach for Zfh when half precision is enough and Zfinx when silicon area is precious; choose hard-float or soft-float to match your hardware. It is all IEEE 754, so your numbers behave — and you only pay, in transistors and power, for the precision you actually use. That right-sizing is precisely why RISC-V scales from a sensor to a supercomputer.
Part of my RISC-V series. See also ISA extensions explained and the vector extension.
