Is RISC-V used in real embedded products today?

Yes, massively. RISC-V already ships in billions of embedded cores — Espressif's ESP32-C Wi-Fi/Bluetooth microcontrollers, storage and power-management controllers inside larger chips, and ultra-cheap WCH CH32V parts. Embedded is RISC-V's most mature market.

What ISA should an embedded RISC-V chip use?

Common embedded configurations are RV32IMC (integer, multiply, compressed) for general microcontrollers, sometimes with F for floating point, or the reduced RV32E base with 16 registers for the smallest, lowest-power cores. Compressed instructions (C) are nearly universal for code density.

How do I start developing for a RISC-V microcontroller?

Pick a board like an ESP32-C6 (ESP-IDF toolchain) or a WCH CH32V part, install a bare-metal newlib RISC-V toolchain (riscv-none-elf or riscv64-unknown-elf), and flash firmware over USB. You can also prototype logic in QEMU before touching hardware.

RISC-V for Embedded and IoT: The MCU Guide

The headlines go to RISC-V servers and AI accelerators, but the place RISC-V already dominates is much smaller: the embedded microcontroller. Billions of RISC-V cores are already in the field — in Wi-Fi chips, storage controllers, and power-management units. This guide is a practical introduction to RISC-V for embedded and IoT.

The DeepComputing booth — Turning RISC-V into Reality — at the Summit

Why RISC-V Won Embedded First

Embedded was the natural beachhead for an open ISA:

No royalties — on parts that sell for cents and ship in the billions, eliminating per-unit license fees is decisive.
Tiny, tailored cores — the modular ISA lets a designer build the smallest core that does the job (often just RV32IMC), saving silicon area and power.
Customization — add a domain-specific instruction for a sensor, motor-control, or DSP loop without licensing friction.
No MMU required — embedded systems use PMP for isolation instead of full virtual memory.

The result: RISC-V quietly became the control core inside countless chips, often invisible to the end user.

The Embedded ISA: Small by Design

Embedded RISC-V configurations strip the ISA to essentials:

RV32I — 32-bit integer base, the embedded starting point.
RV32E — a reduced base with 16 registers instead of 32, for the smallest, lowest-power cores.
M — multiply/divide, common but not universal.
C — compressed instructions, almost always present for code density.
F — single-precision float, added only when the application needs it.

So a typical microcontroller is RV32IMC or RV32EC. There is no D (double float), no V (vectors), no H (hypervisor) — none of the application-class machinery. Embedded RISC-V also has its own RVM profiles to standardize these baselines, the embedded cousins of RVA23.

The Privilege Model for MCUs

Many microcontrollers implement only Machine mode (M), or M + User (U). With no supervisor mode and no MMU, isolation comes from Physical Memory Protection (PMP): M-mode firmware defines regions and permissions, sandboxing untrusted code or protecting a secure region. It is a lightweight, deterministic alternative to virtual memory — ideal for real-time and safety contexts.

The Hardware: What to Buy

A tour of the most accessible RISC-V embedded silicon in 2026:

Espressif ESP32-C Series

The ESP32-C3 / C6 are the gateway drug of RISC-V embedded: cheap, RISC-V-based MCUs with Wi-Fi and Bluetooth, a mature SDK (ESP-IDF), and huge community support. The C6 adds Wi-Fi 6 and Thread/Zigbee. If you are building a connected IoT device, this is the easiest start.

WCH CH32V Series

The WCH CH32V parts are famous for being extraordinarily cheap RV32 microcontrollers — pennies per chip. They are perfect for learning bare-metal RISC-V, hobby projects, and high-volume cost-sensitive designs.

SiFive, Microchip, and FPGA SoftCores

For more serious or mixed designs:

Microchip PolarFire SoC pairs RISC-V application cores with an FPGA fabric.
SiFive offers a range of embedded IP cores.
Open-source softcores (like CVA6 or smaller cores) can be synthesized onto an FPGA — a great way to learn the microarchitecture.

Getting Started: The Toolchain

Embedded means bare-metal, so you want the newlib toolchain, not the Linux/glibc one (see Build a RISC-V Toolchain):

# A bare-metal RISC-V toolchain (package name varies)
sudo apt install -y gcc-riscv64-unknown-elf
# or use the xPack riscv-none-elf-gcc distribution

For the ESP32-C, install ESP-IDF, which bundles its own RISC-V toolchain:

git clone --recursive https://github.com/espressif/esp-idf.git
cd esp-idf && ./install.sh esp32c6
. ./export.sh
idf.py create-project blink && cd blink
idf.py set-target esp32c6
idf.py build flash monitor

For a generic bare-metal target, you compile to an ELF, convert to a binary, and flash with the vendor tool:

riscv64-unknown-elf-gcc -march=rv32imc -mabi=ilp32 -nostdlib \
  -T link.ld -o firmware.elf startup.S main.c
riscv64-unknown-elf-objcopy -O binary firmware.elf firmware.bin
# then flash firmware.bin with the vendor's programmer

Real-Time and RTOS Support

RISC-V is well supported by the embedded software stack:

FreeRTOS, Zephyr, and ThreadX all have RISC-V ports.
Zephyr in particular has strong RISC-V support and is a great choice for portable IoT firmware.
For the smallest jobs, bare-metal with a simple interrupt handler is perfectly viable.

Prototyping Without Hardware

You can model embedded logic in QEMU before flashing real silicon — QEMU has machine models for several embedded boards, and you can run bare-metal ELFs with qemu-system-riscv32. It is not a substitute for on-target timing tests, but it is excellent for developing logic. See my QEMU guide.

Where Embedded RISC-V Is Heading

Two trends stood out at the Summit. First, edge AI: heterogeneous SoCs that pair tiny RISC-V cores with NPUs to run inference within milliwatts — from smart glasses to environmental sensors (the AI accelerator story at the small end). Second, safety-critical embedded: automotive and industrial designs adopting RISC-V with functional-safety rigor.

The Bottom Line

If you want to touch RISC-V today, embedded is the easiest and cheapest entry point. Grab an ESP32-C6 or a CH32V, install a bare-metal toolchain, and flash your first firmware this afternoon. It is also where RISC-V is already winning at scale — billions of cores, no royalties, perfectly tailored silicon. The servers are the future; embedded is the present.

Part of my RISC-V series. Next: RISC-V Open-Source Cores and the 2026 dev boards guide.