For years the standard caveat about RISC-V was “great for embedded, not ready for servers.” In 2026 that caveat no longer holds. At RISC-V Summit Europe 2026, the datacenter story was front and center: production cloud servers, 64-core CPUs, real HPC results, and a strategic push toward sovereign AI. Here is where server-grade open silicon actually stands.
RISC-V Servers You Can Rent Today
The clearest signal that RISC-V has reached the datacenter is that you can rent one. Scaleway’s EM-RV1 is the first RISC-V server available in the public cloud, built from compute modules based on the T-Head TH1520 SoC. This is not a lab prototype — it is production infrastructure with a price tag.
On the silicon side, ESWIN showed its RV23-based RISC-V server CPU explicitly targeting AI factories, cloud infrastructure, and sovereign AI. Ventana continues to push its Veyron server-class cores, and SiFive’s P-series aims at the same high-performance tier. The message: multiple credible vendors now treat the datacenter as a primary RISC-V market, not an afterthought.
The 64-Core Generation
The workhorse of RISC-V server experimentation has been the SG2042 — a 64-core CPU built on T-Head C920 cores that powers the Milk-V Pioneer workstation and several research clusters. Its successor, the SG2044, adds RVV 1.0 vector support and meaningfully higher per-core performance.
These chips matter because they make RISC-V self-hosting at scale: you can compile large software, run databases, and host containers natively, without cross-compiling from x86. That closes a critical loop for the ecosystem.
HPC: The Monte Cimone Result
The most striking datacenter evidence at the Summit came from Monte Cimone v3, the RISC-V HPC cluster from the University of Bologna, E4, CINECA, and ETH Zurich. Built on the SG2044 platform with RVV 1.0, MCv3:
- More than doubles single-core performance over MCv2
- Delivers a 139× speedup over the original Monte Cimone with 10× better energy efficiency
- At 16 cores, reaches roughly 91% of NVIDIA Grace and 46% of Intel normalized performance
- Hits 68% and 80% of their respective energy efficiency
For a server ecosystem this young, getting within striking distance of established HPC silicon — especially on energy efficiency — is a genuine milestone. The PULP platform research from ETH Zurich and Bologna underpins much of this momentum.
Why the Datacenter Cares: Sovereign AI
The strongest pull into the datacenter is not raw benchmarks — it is sovereignty. AI infrastructure has become strategic national capability, and depending on a single foreign vendor for that capability is now seen as a risk.
RISC-V answers that directly. Because the ISA is open and royalty-free:
- Nations can design and manufacture AI silicon without licensing permission
- Supply chains can be built regionally, insulated from export controls
- The hardware can be audited end to end — no proprietary black box
This is why “sovereign AI” appeared in talk after talk at the Summit, from ESWIN’s AI-factory positioning to European initiatives. I dig into the European dimension specifically in RISC-V and European Digital Sovereignty.
The Software Stack Is Ready
Server hardware is only useful if the software runs. In 2026 the stack is in good shape:
- Linux has upstream RISC-V support, and the RVA23 profile gives OS vendors a stable target
- openEuler shipped the first LTS with RVA23 support and is building a RISC-V server OS with ecosystem partners (RVCK, XiangShan pre-silicon validation, a 2026 roadmap toward the RISC-V Server Platform Specification)
- Debian, Ubuntu, and Fedora all maintain RISC-V ports
- Container runtimes, language toolchains, and the cloud-native stack increasingly build cleanly on RV64
The RISC-V Server Platform Specification work is the connective tissue here — a standardized boot, firmware, and platform contract (RVA23 + UEFI/ACPI via BRS + SBI) so that one OS image boots across compliant server hardware, just as it does on x86 and ARM.
What’s Still Missing
Honesty matters. RISC-V is not yet a drop-in replacement for a top-bin x86 or ARM server:
- Peak single-thread performance still trails the best incumbents
- The proprietary enterprise-software long tail is thinner (though shrinking)
- Volume availability of high-core-count server parts is still ramping
But every one of these gaps is narrower than it was a year ago, and the trajectory is steep — the same pattern I describe in RISC-V vs ARM vs x86.
The Bottom Line
RISC-V in the datacenter is no longer a thought experiment. You can rent a RISC-V cloud server, buy a 64-core workstation, point to real HPC results, and run a mainstream Linux stack — all on open silicon. Combine that with the strategic gravity of sovereign AI, and the datacenter may turn out to be RISC-V’s most consequential frontier.
For the accelerator side of the AI story — Tenstorrent, open silicon, and the AI stack — see RISC-V AI Accelerators and Open Silicon.
