Designing RISC-V Cores with Chisel and Chipyard

One of the most exciting things about RISC-V is that you do not just use the chips — you can design your own. Thanks to an open hardware-design flow built around Chisel and Chipyard, building a RISC-V core has moved from the realm of giant corporations to something students and small teams can genuinely attempt. Here is how that world works.

From Using to Building

Because the RISC-V ISA is open, anyone can implement it — and a rich set of open tools has grown up to make that practical. This is the deepest meaning of “open silicon”: not just open cores you can read, but an open flow you can use to create your own. It is the engine behind education efforts like One Student One Chip.

Chisel: Hardware as a Program

Traditional hardware is described in Verilog or VHDL — capable but verbose and low-level. Chisel (Constructing Hardware In a Scala Embedded Language) takes a different approach: it is a hardware-construction language embedded in Scala. You write generators — programs that produce hardware — rather than hand-coding every wire.

// A trivial Chisel module: a register that adds 1 each cycle
class Counter extends Module {
  val io = IO(new Bundle {
    val out = Output(UInt(8.W))
  })
  val count = RegInit(0.U(8.W))
  count := count + 1.U
  io.out := count
}

Chisel elaborates this into synthesizable Verilog, so it drops into any standard toolchain. The payoff is parameterization: you can generate a whole family of designs (different cache sizes, pipeline widths, numbers of cores) from one description — which is exactly how Berkeley produces the Rocket and BOOM cores.

Chipyard: The Full SoC Framework

A core is not a chip. A real system-on-chip needs caches, interconnect, peripherals, memory controllers, and more. Chipyard — the open framework from UC Berkeley — ties it all together. With Chipyard you can:

• Configure an SoC from a library of cores (Rocket, BOOM), accelerators, and components
• Simulate it (fast functional sims and cycle-accurate RTL sims with Verilator)
• Run it on an FPGA (including cloud-FPGA flows like FireSim for fast, scalable emulation)
• Prepare it for tape-out to actual silicon

It turns “design a chip” from a from-scratch epic into configuring and extending a proven, modular baseline.

The Design Flow, End to End

A typical open RISC-V hardware project moves through these stages:

1. Describe the design in Chisel (or integrate existing IP).
2. Generate Verilog with the Chisel/Chipyard build.
3. Simulate functionally to verify behavior — pair this with the debugging tools you would use on real hardware.
4. Synthesize to an FPGA to run real (if slower) hardware and test with actual software.
5. Tape out to silicon — the big, expensive step, increasingly accessible via shared multi-project wafer runs.

The first four stages cost essentially nothing but time and an FPGA board, which is what makes this so democratizing.

FPGAs: Your Personal Chip Lab

You do not need a fab to run your design. An FPGA reconfigures its logic to become your RISC-V core, letting you boot real firmware and even Linux on hardware you defined. Affordable FPGA boards plus open simulators (Verilator) mean a learner can iterate on a real core from a laptop — then validate against QEMU for functional comparison.

Verification: The Hard Part

Designing hardware is one thing; proving it correct is another — and it is where much of the real engineering lives. The open ecosystem has responded with serious tooling: co-simulation frameworks like DiffTest (which famously uncovered scores of bugs in XiangShan), formal verification, and exhaustive ISA compliance suites. If you build a core, budget most of your effort for verification.

Other Languages and Tools

Chisel is popular but not the only path. SpinalHDL (also Scala-based), classic SystemVerilog, and high-level synthesis flows all build RISC-V hardware. The point is the same: an open ISA has spawned an open, approachable design ecosystem with room for many styles.

The Bottom Line

RISC-V is the first mainstream ISA where designing your own processor is a realistic project for students and small teams. Chisel lets you write hardware as parameterized generators; Chipyard assembles cores, accelerators, and interconnect into a complete SoC you can simulate, run on an FPGA, or tape out. The tools are open, the cores are open, and an FPGA turns your laptop into a chip lab. If you have ever wanted to understand processors from the inside, there has never been a better time — or a better ISA — to build one.

Part of my RISC-V series. See also open-source cores and the assembly tutorial.