When people imagine AI silicon they picture GPUs. But look inside many of the newest AI accelerators and you will find RISC-V cores doing the orchestration. At RISC-V Summit Europe 2026, the open ISA’s role in AI hardware was unmistakable — from datacenter accelerators to ultra-low-power edge chips. Here is why RISC-V is quietly becoming the control plane of AI.
RISC-V as the AI Control Plane
A modern AI accelerator is not one big matrix multiplier. It is a sea of compute units that must be fed, scheduled, and synchronized. That orchestration — moving tensors, running the runtime, managing memory — needs programmable general-purpose cores.
This is where RISC-V fits. Instead of licensing ARM cores for control duties (and paying royalties on every chip), accelerator designers embed RISC-V cores they can customize and extend for their dataflow. The heavy lifting happens in custom tensor/matrix units; the RISC-V cores conduct the orchestra. Crucially, because the cores are RISC-V, designers can add custom instructions for emerging operators without a full hardware redesign — a decisive advantage when AI models evolve faster than fixed-function accelerators can.
Tenstorrent Blackhole: The Flagship Example
The most visible RISC-V AI story is Tenstorrent, the company architected in part by Jim Keller. Their Blackhole p150a was on display at the Summit:
- 120 Tensix cores (the compute fabric)
- 16 large RISC-V cores for control and general compute
- Up to 32 GB GDDR6 memory
- Hundreds of teraFLOPS of throughput in an active-cooled PCIe card
The Tensix architecture is a textbook illustration of the pattern: programmable compute tiles tightly coupled with RISC-V cores, all open and scalable. Tenstorrent has leaned into openness across its stack, which resonates with the broader RISC-V philosophy.
The Vector Extension: AI in the Core
Not all AI runs on dedicated accelerators. The RISC-V Vector extension (RVV 1.0) brings SIMD-style parallelism into the CPU itself, letting general-purpose RISC-V cores accelerate inference and signal processing. This is what makes boards like the Banana Pi BPI-F3 (SpacemiT K1) interesting for on-device AI, and it is central to RISC-V’s HPC results.
The ecosystem is also standardizing matrix extensions — IME (Integrated Matrix Extensions) and VME (Vector Matrix Extensions) are converging toward specification freeze, with a unified LLVM/MLIR lowering path so AI frameworks can target both. In other words, matrix math is becoming a first-class, open part of the ISA rather than a proprietary bolt-on.
Edge AI: Doing More With Milliwatts
At the other end of the spectrum, RISC-V dominates the conversation about ultra-low-power edge AI. A recurring Summit theme — from smart-glasses silicon to environmental sensors — was running multiple AI workloads simultaneously within tens of milliwatts.
The winning pattern is heterogeneous SoCs: dedicated NPUs handle well-characterized inference, while programmable RISC-V cores manage pre/post-processing and new operator types. Because those cores are RISC-V, their ISA can be extended with custom instructions to cover emerging operators without re-spinning the chip. Years of open, validated, ultra-low-power microarchitecture research (much of it from the PULP platform at ETH Zurich and Bologna) lower the barrier to building this kind of custom silicon.
Open Hardware Meets Open Models
There is a philosophical symmetry worth naming: open models running on open silicon. I explored the practical end of this in running OpenClaw and Ollama on RISC-V — local LLMs on a fully open stack. It is not fast yet, but it is a statement: the entire pipeline, from ISA to inference, can be free and auditable.
At the agentic end, projects showcased at the Summit are open-sourcing full-stack “agentic SoC” designs — many-core RISC-V fabrics where models, in effect, define the hardware. The open ecosystem lets developers co-design across RTL, compiler, and runtime without vendor constraints.
Why This Matters Strategically
The AI accelerator market is enormously valuable and, today, concentrated. RISC-V offers a path to diversify it:
- No licensing gatekeeper on the control-plane cores
- Customization for rapidly evolving AI operators
- Sovereign AI — designing accelerators without foreign dependency, the theme driving RISC-V into the datacenter and European chip strategy
- A shared software ecosystem so investment compounds across the industry
The Bottom Line
RISC-V may not be the brand on the AI chip, but it is increasingly the architecture inside it — orchestrating Tensix tiles, running edge NPUs, and carrying new open matrix and vector extensions. As AI hardware fragments into ever more specialized designs, an open, extensible ISA is exactly the kind of stable foundation the industry needs. The accelerator wars are far from over, and RISC-V has quietly positioned itself in the middle of them.
I saw this hardware firsthand in Bologna — read the full RISC-V Summit Europe 2026 highlights and the open hardware meets AI deep dive.
