Running a 7-billion-parameter language model on a laptop without a GPU, without a cloud subscription, and without any internet connection. On a RISC-V CPU.
That is what Amir and Federico from DeepComputing demonstrated live at the RISC-V Summit Europe 2026 in Bologna — and it is one of those demos where you watch it happen and recalibrate what you thought the hardware was capable of.
The DC-ROMA Mainboard for Framework 13
The hardware in question is the DC-ROMA RISC-V Mainboard III, a drop-in replacement mainboard for the Framework Laptop 13. The key insight behind the product is that Framework’s modular, open design makes it possible to swap the entire compute board — meaning you can turn a standard Framework laptop into a RISC-V machine without changing the chassis, screen, battery, or keyboard.
The mainboard is built around the SpacemiT K3 SoC, a chip with a deliberately heterogeneous core layout:
| Core type | Count | Purpose |
|---|---|---|
| General-purpose RISC-V cores | 8 | Standard workloads, OS, applications |
| AI-acceleration cores | 8 | Matrix operations, inference |
The AI cores implement the RISC-V Vector Extension (RVV) and are designed to accelerate the kinds of matrix multiplications that dominate large language model inference. Total core count: 16, all RISC-V, all on a single SoC that fits inside a laptop-class thermal envelope.
The Demo: DeepSeek-7B, Live Token Generation
At the summit booth, the team was running DeepSeek-7B — a 7-billion-parameter language model — entirely on the DC-ROMA’s CPU. No GPU. No NPU attached via USB. No offloading to the cloud.
The model was generating tokens in real time during the conversation. You could watch the output stream as the SoC processed the inference request. It is not fast by GPU standards — token-per-second rates on a laptop CPU are modest — but the point is not speed. The point is that it works, and it works on a fully open architecture.
For context: running a 7B model in full precision (FP32) requires roughly 28 GB of memory. Most laptop-class inference uses 4-bit or 8-bit quantization to get this down to 4–7 GB — a range that fits comfortably in the K3’s memory configuration. The AI acceleration cores handle the quantized matrix math efficiently enough to make real-time token generation viable.
Why This Matters
There are a few different lenses through which to read this demo.
The software stack lens. Getting a modern LLM to run on RISC-V hardware requires a complete software stack: a runtime that supports RVV for vectorized inference (llama.cpp, with RISC-V support, is the most common path), driver support in the OS, and a working toolchain to compile it all for the target ISA. The fact that DeepComputing can run DeepSeek on this hardware reflects years of work on the RISC-V software ecosystem, not just silicon engineering. This is the same hardware stack that has also successfully run Triton — NVIDIA’s GPU programming language — on RISC-V, which was announced separately at the summit.
The sovereignty lens. Running AI locally on a RISC-V chip closes the loop on a question that has become increasingly important: what does it mean to run AI on genuinely open hardware? The ISA is open. The chip architecture is published. The software is open source. There is no proprietary instruction set, no closed firmware blob, no vendor dependency beyond the hardware itself. For organizations operating in environments where data residency and hardware provenance matter — defense, healthcare, critical infrastructure — this is not an abstract concern.
The RISC-V maturity lens. A few years ago, the realistic ceiling for RISC-V at the edge was microcontrollers and embedded systems. Server-grade RISC-V was a research project. The idea of running a 7B language model on a RISC-V laptop would have been a conference keynote prediction, not a live booth demo. The DC-ROMA demo is a data point in a much larger story: the RISC-V ecosystem in 2026 spans embedded, laptop, and server-grade silicon from dozens of vendors. The trajectory is no longer speculative.
The Framework Advantage
The choice of Framework Laptop as the chassis is not incidental. Framework’s philosophy — modular, repairable, open — aligns naturally with what RISC-V represents in silicon. A proprietary laptop would require a custom enclosure, a custom power delivery system, and a manufacturer willing to commit resources to a niche market. Framework’s modular design sidesteps all of that: the mainboard connector is documented, the chassis is widely available, and existing owners can upgrade by swapping the board.
It also means the DC-ROMA benefits from Framework’s existing ecosystem: the keyboard, trackpad, display, and expansion cards all work unchanged. For a team building a niche RISC-V laptop product, that is an enormous reduction in the hardware design surface.
Related Coverage from RISC-V Summit Europe 2026
- EPIC Semi’s First RISC-V AI Server Runs Ubuntu
- One Student One Chip: Free Tapeouts for RISC-V Education
- Red Hat at RISC-V Summit: Kubernetes Meets Open Silicon
- RISC-V Summit Europe 2026: Bologna Highlights
- Running Local AI with Ollama on RISC-V Hardware
About the Author
I am Luca Berton, AI and Cloud Advisor. I design AI infrastructure for enterprises navigating the shift from cloud-only to hybrid and on-premises deployments. Book a consultation.
