A real server. A real operating system. And another important step toward RISC-V-powered AI infrastructure. At RISC-V Summit Europe 2026 in Bologna, I spoke with Chloe Jian Ma, Chief Business Officer at EPIC Semi, about what the company describes as the first AI server built on RISC-V.
A RISC-V AI Server — Running Ubuntu
Earlier that same day, the EPIC Semi team had successfully brought up Ubuntu on the system — a significant milestone for its CPU-plus-AI architecture. Getting a full general-purpose Linux distribution booting on new silicon is the moment a research project starts to look like a real product: it means the software porting and boot flow work, and that developers can treat the machine like any other server.
Inside the Chip
The standout part of the EPIC Semi design is how tightly it fuses general-purpose compute and AI acceleration on one die:
- 48 cores clocked at 2.2 GHz
- 32 high-performance RISC-V cores supporting RVV 1.0
- 16 dedicated AI cores
- 512-bit vector length on the AI cores
- Vector Matrix Extension for hardware-accelerated matrix operations
- Shared cache, memory and storage across the CPU and AI cores
That shared-resource design is the interesting architectural bet. Because the high-performance and AI cores exchange data and context through the same memory and cache, they can hand work back and forth efficiently — without the cost of shuttling data across a completely separate GPU architecture and its own memory pool.
Why CPU-Plus-AI Integration Matters
Most AI infrastructure today bolts a discrete accelerator onto a host CPU, and the connection between them is often the bottleneck. EPIC Semi’s approach keeps the AI accelerator and the CPU on the same tightly integrated fabric. For workloads that constantly move between general-purpose logic and matrix math — exactly what serving a language model looks like — that integration can pay off in both latency and efficiency.
The Vector Matrix Extension is the engine here: matrix multiply is the dominant operation in transformer inference, and putting it in hardware close to the cores is what makes a CPU-centric design competitive for AI.
Built for Sovereign, Private AI
EPIC Semi sees this as a compelling approach for enterprise generative AI, particularly for running private small and medium-sized language models while supporting greater control, security and technological sovereignty.
That framing fits the broader European story I keep hearing at the Summit. Running your own models, on your own datacenter silicon, built on an open ISA, is one of the most direct answers to the digital-sovereignty question — reducing dependence on foreign, proprietary architectures for strategic AI infrastructure.
The Bottom Line
EPIC Semi’s server is a concrete data point in a story that is moving fast: RISC-V is no longer just for microcontrollers and research clusters — it is showing up as real datacenter and AI infrastructure. A 48-core chip blending 32 RVV 1.0 cores with 16 AI cores, a Vector Matrix Extension, shared memory across the whole design, and Ubuntu booting on the bench — that is a meaningful step. Whether the integrated CPU-plus-AI approach wins out over discrete accelerators is the open question, but it is exactly the kind of bet an open, customizable ISA makes possible.
Great to catch up with Chloe and the EPIC Semi team in Bologna. Learn more at epicsemi.com.
Interview recorded at RISC-V Summit Europe 2026, Bologna, Italy, 8–12 June 2026. Part of my RISC-V series — see also the Summit highlights and RISC-V datacenter & sovereign AI.
