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RISC-V

All posts in the "RISC-V" category

Everything RISC-V — the free, open instruction set architecture. Deep dives on the ISA and extensions, dev boards, toolchains, Linux, embedded and datacenter silicon, security, and the open-hardware ecosystem, plus conference coverage.

Browse the 50 RISC-V articles below. Written by Luca Berton — Docker Captain, author of 8 technical books on Ansible, and an AI & Cloud Advisor with 15+ years of enterprise experience — each post covers practical risc-v techniques, real-world troubleshooting, and production-grade best practices for engineers, SREs, platform teams, and technical leaders.

Whether you are looking for a quick command reference, a deep-dive tutorial, a step-by-step error fix, or strategic guidance, the RISC-V category aggregates hands-on guides, benchmarks, conference recaps, and architectural insights drawn from real customer engagements and open-source projects. New articles are published regularly — bookmark this page or subscribe to the RSS feed to stay up to date.

Explore related categories: ai, AI, Automation, Books and Community, Conferences, database, design, DevOps.

Every RISC-V article on this page is written from first-hand experience — deployed in production, debugged under real constraints, and distilled into clear, reproducible steps. Expect copy-paste-ready commands, annotated configuration, decision frameworks comparing the trade-offs of competing tools, and the context you need to choose the right approach for your environment rather than a one-size-fits-all recipe. The goal is simple: help you ship risc-v work that is correct, secure, and maintainable.

Recent RISC-V posts include DeepComputing DC-ROMA: Running DeepSeek on a RISC-V Laptop, No GPU, Build a RISC-V Toolchain: GCC and LLVM, Getting Started with RISC-V on QEMU, The History of RISC-V: From Berkeley to the World, Red Hat at RISC-V Summit Europe 2026: Kubernetes Meets Open Silicon. Have a question or a topic you would like covered? Get in touch or connect on the channels linked in the site footer.

  • RISC-V Summit Europe 2026 expo floor in Bologna with DeepComputing among exhibitors
    RISC-V

    DeepComputing DC-ROMA: Running DeepSeek on a RISC-V Laptop, No GPU

    Luca Berton •
  • RISC-V community members and developers at RISC-V Summit Europe 2026
    RISC-V

    Build a RISC-V Toolchain: GCC and LLVM

    Luca Berton •
  • Holding a RISC-V development board at the Summit, representing hands-on RISC-V
    RISC-V

    Getting Started with RISC-V on QEMU

    Luca Berton •
  • The RISC-V community gathered at RISC-V Summit Europe 2026
    RISC-V

    The History of RISC-V: From Berkeley to the World

    Luca Berton •
  • Luca Berton with the RISC-V Summit Europe 2026 sponsor wall in Bologna showing DeepComputing, Epic Semi, ESWIN and other exhibitors
    RISC-V

    Red Hat at RISC-V Summit Europe 2026: Kubernetes Meets Open Silicon

    Luca Berton •
  • RISC-V developers discussing the ABI and toolchain at RISC-V Summit Europe 2026
    RISC-V

    The RISC-V ABI and Calling Convention Explained

    Luca Berton •
  • Breker and Tenstorrent booth at RISC-V Summit Europe 2026
    RISC-V

    RISC-V AI Accelerators and Open Silicon

    Luca Berton •
  • Developers exploring RISC-V technology at RISC-V Summit Europe 2026
    RISC-V

    RISC-V Assembly Tutorial: Your First Program

    Luca Berton •
  • Automotive and safety-focused RISC-V silicon on display at RISC-V Summit Europe 2026
    RISC-V

    RISC-V in Automotive: Functional Safety & Quintauris

    Luca Berton •
  • RISC-V hardware and development systems at RISC-V Summit Europe 2026
    RISC-V

    RISC-V Boot Flow: OpenSBI, U-Boot & the SBI

    Luca Berton •
  • RISC-V chip design and FPGA development at RISC-V Summit Europe 2026
    RISC-V

    Designing RISC-V Cores with Chisel and Chipyard

    Luca Berton •
  • Cloud-native and Kubernetes on RISC-V discussion at RISC-V Summit Europe 2026
    RISC-V

    Running Containers and Kubernetes on RISC-V

    Luca Berton •
  • RISC-V security and cryptography hardware at RISC-V Summit Europe 2026
    RISC-V

    RISC-V Cryptography: Scalar and Vector Crypto

    Luca Berton •
  • ESWIN booth showing the world's first RV23-based RISC-V AI super chip
    RISC-V

    RISC-V in the Datacenter: Servers & Sovereign AI

    Luca Berton •
  • RISC-V development hardware at RISC-V Summit Europe 2026
    RISC-V

    Debugging RISC-V: GDB, OpenOCD and JTAG

    Luca Berton •
  • A showcase table of RISC-V development boards at RISC-V Summit Europe 2026
    RISC-V

    RISC-V Development Boards: 2026 Buyer's Guide

    Luca Berton •
  • Industry leaders and vendors at RISC-V Summit Europe 2026
    RISC-V

    The RISC-V Business Case: Why Royalty-Free Wins

    Luca Berton •
  • The BOSC and XiangShan booth at RISC-V Summit Europe 2026
    RISC-V

    The RISC-V Ecosystem in 2026

    Luca Berton •
  • DeepComputing booth — Turning RISC-V into Reality — at RISC-V Summit Europe 2026
    RISC-V

    RISC-V for Embedded and IoT: The MCU Guide

    Luca Berton •
  • Embedded Rust development on RISC-V hardware at RISC-V Summit Europe 2026
    RISC-V

    Embedded Rust on RISC-V: A Practical Guide

    Luca Berton •
  • A Realising the Future of Europe panel on the main stage at RISC-V Summit Europe 2026
    RISC-V

    RISC-V and European Digital Sovereignty

    Luca Berton •
  • RISC-V floating-point and numerical computing discussion at RISC-V Summit Europe 2026
    RISC-V

    RISC-V Floating-Point Extensions: F, D, Q and More

    Luca Berton •
  • Close-up of an ESWIN RISC-V AI chip, illustrating ISA extensions in silicon
    RISC-V

    RISC-V Extensions Explained: The ISA Alphabet

    Luca Berton •
  • RISC-V softcore running on an FPGA board at RISC-V Summit Europe 2026
    RISC-V

    Build a RISC-V Softcore on an FPGA

    Luca Berton •
  • High-performance RISC-V computing systems at RISC-V Summit Europe 2026
    RISC-V

    RISC-V in HPC: Supercomputing on Open Silicon

    Luca Berton •
  • RISC-V silicon and systems on display at RISC-V Summit Europe 2026
    RISC-V

    RISC-V Interrupts: CLINT, PLIC and the AIA

    Luca Berton •
  • RISC-V systems running Linux on display at RISC-V Summit Europe 2026
    RISC-V

    Running Linux on RISC-V: Ubuntu, Fedora & Debian

    Luca Berton •
  • Multi-core RISC-V systems at RISC-V Summit Europe 2026
    RISC-V

    The RISC-V Memory Model: RVWMO and Atomics

    Luca Berton •
  • The BOSC XiangShan booth at RISC-V Summit Europe 2026
    RISC-V

    RISC-V Open-Source Cores: CVA6, XiangShan & More

    Luca Berton •
  • RISC-V performance engineering and profiling session at RISC-V Summit Europe 2026
    RISC-V

    Performance Profiling and Counters on RISC-V

    Luca Berton •
  • A keynote on the main stage at RISC-V Summit Europe 2026 with the RISC-V logo
    RISC-V

    RISC-V Profiles and RVA23 Explained

    Luca Berton •
  • Post-quantum cryptography research poster at RISC-V Summit Europe 2026
    RISC-V

    RISC-V Security: Privilege, PMP & Confidential Computing

    Luca Berton •
  • RISC-V software and tooling showcased at RISC-V Summit Europe 2026
    RISC-V

    Porting Software to RISC-V: A Practical Guide

    Luca Berton •
  • Specialized RISC-V silicon on display at RISC-V Summit Europe 2026
    RISC-V

    RISC-V in Space: Radiation-Hardened Open Silicon

    Luca Berton •
  • Tape-out RISC-V chips, representing vector-capable silicon
    RISC-V

    RISC-V Vector Programming with RVV 1.0

    Luca Berton •
  • RISC-V server and datacenter hardware at RISC-V Summit Europe 2026
    RISC-V

    RISC-V Virtualization: The H Extension & KVM

    Luca Berton •
  • Close-up of a RISC-V chip module compared against other architectures
    RISC-V

    RISC-V vs ARM vs x86: How the Open ISA Compares

    Luca Berton •
  • Zephyr RTOS running on RISC-V boards at RISC-V Summit Europe 2026
    RISC-V

    Running Zephyr RTOS on RISC-V

    Luca Berton •
  • RISC-V development boards on display at RISC-V Summit Europe 2026 Bologna expo floor
    RISC-V

    SemiTo-V: The Student RISC-V FPGA Board That Got Manufactured

    Luca Berton •
  • A RISC-V development board with a Join the RISC-V Revolution sign
    RISC-V

    What Is RISC-V? The Open ISA Explained

    Luca Berton •
  • EPIC Semi RISC-V AI server running Ubuntu at RISC-V Summit Europe 2026
    RISC-V

    EPIC Semi's RISC-V AI Server Runs Ubuntu

    Luca Berton •
  • Business-strategy conversation at RISC-V Summit Europe 2026 in Bologna
    RISC-V

    Why 9 in 10 High-Tech Startups Stall

    Luca Berton •
  • High-performance RISC-V booths at RISC-V Summit Europe 2026 in Bologna
    RISC-V

    InspireSemi & NextSilicon: RISC-V HPC

    Luca Berton •
  • OmniTrust at RISC-V Summit Europe 2026 — trust infrastructure for AI
    RISC-V

    OmniTrust: Visibility & Control for AI

    Luca Berton •
  • One Student One Chip Learning Roadmap at RISC-V Summit Europe 2026
    RISC-V

    One Student One Chip: 18,861 Students Build RISC-V Chips

    Luca Berton •
  • Luca Berton at RISC-V Summit Europe 2026 expo floor in Bologna
    RISC-V

    RISC-V Summit Europe 2026: Hardware Innovation from Bologna

    Luca Berton •
  • RISC-V Summit Europe 2026 Bologna
    RISC-V

    RISC-V Summit Europe 2026: Open Hardware Meets AI in Bologna

    Luca Berton •
  • RISC-V hardware from dev boards to AI servers at RISC-V Summit Europe 2026 in Bologna
    RISC-V

    RISC-V: From Dev Boards to AI Servers

    Luca Berton •
  • Book signing at RISC-V Summit Europe 2026 in Bologna, Italy
    RISC-V

    Book Signing at RISC-V Summit Europe 2026 in Bologna

    Luca Berton •
  • Running OpenClaw + Ollama on RISC-V
    RISC-V

    Running OpenClaw + Ollama on RISC-V: Local LLMs on Open...

    Luca Berton •

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