Blog
1645+ articles — Page 8 of 69
RISC-V Security: Privilege, PMP & Confidential Computing
How RISC-V handles security — machine/supervisor/user privilege, Physical Memory Protection, the hypervisor extension, and confidential computing.
4 min read
Porting Software to RISC-V: A Practical Guide
How to port applications and libraries to RISC-V — cross-compiling, common pitfalls, intrinsics, CI, and the state of the riscv64 software ecosystem in 2026.
4 min read
RISC-V Vector Programming with RVV 1.0
A hands-on introduction to the RISC-V Vector extension (RVV 1.0) — the vector-length-agnostic model, key instructions, and a worked SAXPY example you can run.
5 min read
What Is RISC-V? The Open ISA Explained
A plain-English introduction to RISC-V — the free, open instruction set architecture reshaping chips from microcontrollers to datacenter servers.
6 min read
The History of RISC-V: From Berkeley to the World
Where did RISC-V come from? The story from a 2010 Berkeley summer project to a global open standard — the people, the philosophy, and why it succeeded.
3 min read
The RISC-V ABI and Calling Convention Explained
How RISC-V code actually fits together — registers, the psABI, argument passing, the stack, and ILP32 vs LP64. A practical guide to the calling convention.
4 min read
Designing RISC-V Cores with Chisel and Chipyard
Want to build your own RISC-V chip? An intro to Chisel, Chipyard, and the open hardware-design flow — from RTL generators to an FPGA or tape-out. Start here.
4 min read
Running Containers and Kubernetes on RISC-V
Yes, RISC-V runs Docker and Kubernetes. How container images, multi-arch builds, and the cloud-native stack work on RISC-V — and what's still maturing.
3 min read
RISC-V Cryptography: Scalar and Vector Crypto
How RISC-V accelerates cryptography — the scalar crypto (Zk) and vector crypto extensions, AES/SHA instructions, constant-time guarantees, and entropy sources.
4 min read
The RISC-V Business Case: Why Royalty-Free Wins
The economics behind RISC-V — royalty-free licensing, supply-chain control, customization, and why the business case (not just the tech) is driving adoption.
4 min read
Embedded Rust on RISC-V: A Practical Guide
Rust and RISC-V are a natural pair. How to write embedded Rust for RISC-V microcontrollers — targets, no_std, PACs, HALs, and flashing real hardware.
3 min read
RISC-V Floating-Point Extensions: F, D, Q and More
How RISC-V does floating-point — the F, D, and Q extensions, the f registers, rounding modes, and lightweight options like Zfh and Zfinx for small cores.
3 min read
Build a RISC-V Softcore on an FPGA
Turn a cheap FPGA into a real RISC-V CPU. A practical intro to softcores like PicoRV32 and VexRiscv — what they are, how the flow works, and how to start.
3 min read
RISC-V in HPC: Supercomputing on Open Silicon
RISC-V is heading for the supercomputer — Monte Cimone, the European Processor Initiative, and what it takes to build HPC on an open ISA.
4 min read
The RISC-V Memory Model: RVWMO and Atomics
Understand the RISC-V memory model (RVWMO), atomic instructions, LR/SC, and fences. A practical guide to concurrency and lock-free programming on RISC-V.
4 min read
Performance Profiling and Counters on RISC-V
Make RISC-V code fast — hardware performance counters (HPM), the cycle and instret CSRs, perf on Linux, and a sane workflow for finding real bottlenecks.
3 min read
RISC-V in Space: Radiation-Hardened Open Silicon
Why space agencies are adopting RISC-V — NASA's HPSC, radiation hardening, fault tolerance, and the case for an open ISA in satellites and spacecraft.
4 min read
RISC-V Virtualization: The H Extension & KVM
How virtualization works on RISC-V — the hypervisor (H) extension, two-stage translation, KVM, and running virtual machines on open silicon. A systems guide.
4 min read
RISC-V vs ARM vs x86: How the Open ISA Compares
How RISC-V stacks up against ARM and x86 on licensing, performance, software maturity, and customization — and where each architecture wins in 2026.
5 min read
Running Zephyr RTOS on RISC-V
Zephyr is the open RTOS of choice for modern RISC-V microcontrollers. What Zephyr is, why it fits RISC-V, and how its build and driver model work.
3 min read
One Student One Chip: 18,861 Students Build RISC-V Chips
BOSC's One Student One Chip teaches students to design RISC-V processors from ISA to GDSII tape-out. At RISC-V Summit Europe 2026, 18,861 enrollments revealed.
9 min read
RISC-V Summit Europe 2026: Hardware Innovation from Bologna
My experience at RISC-V Summit Europe 2026 in Bologna — from Tenstorrent Blackhole to Monte Cimone v3 HPC, ESWIN server CPUs, and open-silicon research.
13 min read
RISC-V Summit Europe 2026: Open Hardware Meets AI in Bologna
On-the-ground coverage from RISC-V Summit Europe 2026 in Bologna — SiFive, ETH Zurich, Qualcomm, and Luxottica on open silicon for AI and smart eyewear.
14 min read
Reliable AI Agents in Java with LangChain4J — Workshop
Packt workshop with Susanne Pieterse on building production-ready AI agents in Java with LangChain4J — guardrails, evaluation, observability. June 13, 2026.
2 min read