Blog
1574+ articles — Page 4 of 66
OpenClaw Backup and Reinstall: Preserve Config, Memory, and Credentials
How to back up OpenClaw before a clean reinstall, preserve ~/.openclaw state, restore config and memory, and avoid copying caches or exposed secrets.
8 min read
Restore a Deleted Google Analytics 4 Property
Deleted a GA4 property by mistake? Restore it from Google Analytics Trash within 35 days and keep the original measurement ID.
3 min read
Auth0 for AI Agents: Identity, Compliance, and Access Control
How Auth0 for AI Agents helps secure GenAI applications with authentication, delegated API access, and fine-grained authorization for RAG.
7 min read
Differential Privacy: How Math Protects Your Privacy
How differential privacy uses intelligent noise to protect personal data without losing its value — explained at the ing.tonic. talk in Padova.
7 min read
GLM-5.2 744B: Sparse Attention Meets Efficient MoE
GLM-5.2 is a 744B-parameter MoE model with DeepSeek Sparse Attention, 256 experts (8+1 active), 40B active params per step, and a 1M-token context window.
5 min read
DeepComputing DC-ROMA: Running DeepSeek on a RISC-V Laptop, No GPU
At RISC-V Summit Europe 2026 in Bologna, DeepComputing ran a 7B DeepSeek model on their DC-ROMA Framework 13 mainboard — 100% on CPU, no cloud, no GPU.
4 min read
Red Hat at RISC-V Summit Europe 2026: Kubernetes Meets Open Silicon
Met Brian Harrington from Red Hat at RISC-V Summit Europe 2026 in Bologna. The intersection of RISC-V and cloud-native Kubernetes is no longer theoretical.
4 min read
SemiTo-V: The Student RISC-V FPGA Board That Got Manufactured
At RISC-V Summit Europe 2026, Dan showed the SemiTo-V student team's Gowin FPGA + RP2350 board — designed by students, assembled free via NextPCB's program.
4 min read
Build a RISC-V Toolchain: GCC and LLVM
How to build or install a RISC-V cross-compiler with GCC and LLVM/Clang — newlib vs glibc, multilib, and compiling your first RV64 binary from scratch.
4 min read
Getting Started with RISC-V on QEMU
Emulate a full RISC-V Linux system on your laptop with QEMU — no hardware required. A step-by-step guide to booting Ubuntu and running your first RV64 binary.
4 min read
RISC-V AI Accelerators and Open Silicon
How RISC-V powers modern AI accelerators — from Tenstorrent's Blackhole to edge NPUs — and why the open ISA is becoming the control plane for AI chips.
4 min read
RISC-V Assembly Tutorial: Your First Program
Learn RISC-V assembly from scratch — registers, instruction formats, and a working hello-world you can run in QEMU. A beginner-friendly intro to the open ISA.
4 min read
RISC-V in Automotive: Functional Safety & Quintauris
Why carmakers are betting on RISC-V — Quintauris, functional safety (ISO 26262), mixed-criticality, and what it takes to put an open ISA in a vehicle.
4 min read
RISC-V Boot Flow: OpenSBI, U-Boot & the SBI
How a RISC-V system boots — the SBI, OpenSBI, U-Boot, UEFI, and the journey from reset vector to a running Linux kernel, explained step by step.
4 min read
RISC-V in the Datacenter: Servers & Sovereign AI
RISC-V has reached the datacenter — cloud servers, 64-core CPUs, HPC clusters, and sovereign AI. Here's the state of server-grade open silicon in 2026.
4 min read
Debugging RISC-V: GDB, OpenOCD and JTAG
A practical guide to debugging RISC-V — GDB, OpenOCD, JTAG, the Debug Spec, and single-stepping real hardware or QEMU. From printf to breakpoints.
4 min read
RISC-V Development Boards: 2026 Buyer's Guide
From the VisionFive 2 to the Milk-V Jupiter and Banana Pi BPI-F3 — the best RISC-V development boards to buy in 2026, matched to budget and use case.
4 min read
The RISC-V Ecosystem in 2026
The vendors, profiles, software, and momentum behind RISC-V in 2026 — a map of the open-silicon ecosystem and why it has reached an inflection point.
4 min read
RISC-V for Embedded and IoT: The MCU Guide
RISC-V already ships in billions of embedded cores. A practical guide to RISC-V microcontrollers — ESP32-C, CH32V, PMP, the M-profile, and getting started.
4 min read
RISC-V and European Digital Sovereignty
Why RISC-V is central to Europe's digital sovereignty strategy — from the EU Chips Act and EuroHPC to Quintauris, BSC, and sovereign AI in 2026.
4 min read
RISC-V Extensions Explained: The ISA Alphabet
M, A, F, D, C, V, B, H and the Z-extensions — a clear guide to the RISC-V extension alphabet and how to read strings like RV64GC and rv64imafdc.
5 min read
RISC-V Interrupts: CLINT, PLIC and the AIA
How interrupts work on RISC-V — traps, the CLINT and PLIC, and the modern Advanced Interrupt Architecture (AIA) with MSIs. A guide for systems devs.
4 min read
Running Linux on RISC-V: Ubuntu, Fedora & Debian
Yes, you can run a full Linux desktop and server on RISC-V today. A practical guide to Ubuntu, Fedora, and Debian on RISC-V — and how mature each really is.
3 min read
RISC-V Open-Source Cores: CVA6, XiangShan & More
A tour of the leading open-source RISC-V cores — CVA6, XiangShan, lowRISC Ibex, and the PULP platform — and why open silicon all the way down matters.
4 min read