The Luca Berton Blog
1498+ expert articles on AI, Kubernetes, Ansible, Platform Engineering, and cloud infrastructure — practical, hands-on guides and industry insights from Luca Berton, AI & Cloud Advisor. Explore tutorials, deep dives, and the latest from every topic.
Build a RISC-V Toolchain: GCC and LLVM
How to build or install a RISC-V cross-compiler with GCC and LLVM/Clang — newlib vs glibc, multilib, and compiling your first RV64 binary from scratch.
Getting Started with RISC-V on QEMU
Emulate a full RISC-V Linux system on your laptop with QEMU — no hardware required. A step-by-step guide to booting Ubuntu and running your first RV64 binary.
4 min read
The History of RISC-V: From Berkeley to the World
Where did RISC-V come from? The story from a 2010 Berkeley summer project to a global open standard — the people, the philosophy, and why it succeeded.
3 min read
RISC-V AI Accelerators and Open Silicon
How RISC-V powers modern AI accelerators — from Tenstorrent's Blackhole to edge NPUs — and why the open ISA is becoming the control plane for AI chips.
4 min read
RISC-V Assembly Tutorial: Your First Program
Learn RISC-V assembly from scratch — registers, instruction formats, and a working hello-world you can run in QEMU. A beginner-friendly intro to the open ISA.
4 min read
RISC-V in Automotive: Functional Safety & Quintauris
Why carmakers are betting on RISC-V — Quintauris, functional safety (ISO 26262), mixed-criticality, and what it takes to put an open ISA in a vehicle.
4 min read
RISC-V Boot Flow: OpenSBI, U-Boot & the SBI
How a RISC-V system boots — the SBI, OpenSBI, U-Boot, UEFI, and the journey from reset vector to a running Linux kernel, explained step by step.
4 min read
Designing RISC-V Cores with Chisel and Chipyard
Want to build your own RISC-V chip? An intro to Chisel, Chipyard, and the open hardware-design flow — from RTL generators to an FPGA or tape-out. Start here.
4 min read
RISC-V Cryptography: Scalar and Vector Crypto
How RISC-V accelerates cryptography — the scalar crypto (Zk) and vector crypto extensions, AES/SHA instructions, constant-time guarantees, and entropy sources.
4 min read
RISC-V in the Datacenter: Servers & Sovereign AI
RISC-V has reached the datacenter — cloud servers, 64-core CPUs, HPC clusters, and sovereign AI. Here's the state of server-grade open silicon in 2026.
4 min read
Debugging RISC-V: GDB, OpenOCD and JTAG
A practical guide to debugging RISC-V — GDB, OpenOCD, JTAG, the Debug Spec, and single-stepping real hardware or QEMU. From printf to breakpoints.
4 min read
RISC-V Development Boards: 2026 Buyer's Guide
From the VisionFive 2 to the Milk-V Jupiter and Banana Pi BPI-F3 — the best RISC-V development boards to buy in 2026, matched to budget and use case.
4 min read
The RISC-V Business Case: Why Royalty-Free Wins
The economics behind RISC-V — royalty-free licensing, supply-chain control, customization, and why the business case (not just the tech) is driving adoption.
4 min read
The RISC-V Ecosystem in 2026
The vendors, profiles, software, and momentum behind RISC-V in 2026 — a map of the open-silicon ecosystem and why it has reached an inflection point.
4 min read
RISC-V for Embedded and IoT: The MCU Guide
RISC-V already ships in billions of embedded cores. A practical guide to RISC-V microcontrollers — ESP32-C, CH32V, PMP, the M-profile, and getting started.
4 min read
RISC-V and European Digital Sovereignty
Why RISC-V is central to Europe's digital sovereignty strategy — from the EU Chips Act and EuroHPC to Quintauris, BSC, and sovereign AI in 2026.
4 min read
RISC-V Extensions Explained: The ISA Alphabet
M, A, F, D, C, V, B, H and the Z-extensions — a clear guide to the RISC-V extension alphabet and how to read strings like RV64GC and rv64imafdc.
5 min read
RISC-V in HPC: Supercomputing on Open Silicon
RISC-V is heading for the supercomputer — Monte Cimone, the European Processor Initiative, and what it takes to build HPC on an open ISA.
4 min read
RISC-V Interrupts: CLINT, PLIC and the AIA
How interrupts work on RISC-V — traps, the CLINT and PLIC, and the modern Advanced Interrupt Architecture (AIA) with MSIs. A guide for systems devs.
4 min read
Running Linux on RISC-V: Ubuntu, Fedora & Debian
Yes, you can run a full Linux desktop and server on RISC-V today. A practical guide to Ubuntu, Fedora, and Debian on RISC-V — and how mature each really is.
3 min read
The RISC-V Memory Model: RVWMO and Atomics
Understand the RISC-V memory model (RVWMO), atomic instructions, LR/SC, and fences. A practical guide to concurrency and lock-free programming on RISC-V.
4 min read
RISC-V Open-Source Cores: CVA6, XiangShan & More
A tour of the leading open-source RISC-V cores — CVA6, XiangShan, lowRISC Ibex, and the PULP platform — and why open silicon all the way down matters.
4 min read
RISC-V Profiles and RVA23 Explained
Why RISC-V profiles exist and what RVA23 changes — the standardized extension bundles that make 'write once, run anywhere' real for RISC-V software.
4 min read
RISC-V Security: Privilege, PMP & Confidential Computing
How RISC-V handles security — machine/supervisor/user privilege, Physical Memory Protection, the hypervisor extension, and confidential computing.
4 min read